Datasheet

ManualsBrandsAlliance Memory ManualsDRAMDRAM 8GB 1.25ns TFBGA

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Table Of Contents

DDR3L SDRAM
Description
- FBGA Part Marking Decoder
State Diagram
Functional Description
- Industrial Temperature
- General Notes
Functional Block Diagrams
Ball Assignments and Descriptions
Package Dimensions
Electrical Specifications
- Absolute Ratings
- Input/Output Capacitance
Thermal Characteristics
Electrical Specifications – I DD Specifications and Conditions
Electrical Characteristics – 1.35V IDD Specifications
Electrical Specifications – DC and AC
- DC Operating Conditions
- Input Operating Conditions
- DDR3L 1.35V AC Overshoot/Undershoot Specification
- DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals
- DDR3L 1.35V Slew Rate Definitions for Differential Input Signals
ODT Characteristics
- 1.35V ODT Resistors
- ODT Sensitivity
- ODT Timing Definitions
Output Driver Impedance
- 34 Ohm Output Driver Impedance
- DDR3L 34 Ohm Driver
- DDR3L 34 Ohm Output Driver Sensitivity
- DDR3L Alternative 40 Ohm Driver
- DDR3L 40 Ohm Output Driver Sensitivity
Output Characteristics and Operating Conditions
- Reference Output Load
- Slew Rate Definitions for Single-Ended Output Signals
- Slew Rate Definitions for Differential Output Signals
Speed Bin Tables
Electrical Characteristics and AC Operating Conditions
Electrical Characteristics and AC Operating Conditions
Command and Address Setup, Hold, and Derating
Data Setup, Hold, and Derating
Commands – Truth Tables
Commands
- DESELECT
- NO OPERATION
- ZQ CALIBRATION LONG
- ZQ CALIBRATION SHORT
- ACTIVATE
- READ
- WRITE
- PRECHARGE
- REFRESH
- SELF REFRESH
- DLL Disable Mode
Input Clock Frequency Change
Write Leveling
- Write Leveling Procedure
- Write Leveling Mode Exit Procedure
Initialization
Voltage Initialization / Change
- VDD Voltage Switching
Mode Registers
Mode Register 0 (MR0)
- Burst Length
- Burst Type
- DLL RESET
- Write Recovery
- Precharge Power-Down (Precharge PD)
- CAS Latency (CL)
Mode Register 1 (MR1)
- DLL Enable/DLL Disable
- Output Drive Strength
- OUTPUT ENABLE/DISABLE
- TDQS Enable
- On-Die Termination
- WRITE LEVELING
- POSTED CAS ADDITIVE Latency
Mode Register 2 (MR2)
- CAS WRITE Latency (CWL)
- AUTO SELF REFRESH (ASR)
- SELF REFRESH TEMPERATURE (SRT)
- SRT vs. ASR
- DYNAMIC ODT
Mode Register 3 (MR3)
- MULTIPURPOSE REGISTER (MPR)
- MPR Functional Description
- MPR Register Address Definitions and Bursting Order
- MPR Read Predefined Pattern
MODE REGISTER SET (MRS) Command
ZQ CALIBRATION Operation
ACTIVATE Operation
READ Operation
WRITE Operation
- DQ Input Timing
PRECHARGE Operation
SELF REFRESH Operation
Extended Temperature Usage
Power-Down Mode
RESET Operation
On-Die Termination (ODT)
- Functional Representation of ODT
- Nominal ODT
Dynamic ODT
- Dynamic ODT Special Use Case
- Functional Description
Synchronous ODT Mode
- ODT Latency and Posted ODT
- Timing Parameters
- ODT Off During READs
Asynchronous ODT Mode
- Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry)
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
- Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse)

Figure 58: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout

T0 Ta0 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 Tc10

CK#

MRSPREA

READ

NOPNOP NOP NOP NOP NOP NOP NOP MRS NOP NOP ValidCommand

MPRR

Don’t Care

Indicates break

in time scale

DQS, DQS#

Bank address 3 Valid 3

0A[1:0] Valid

1A2

00A[9:3] Valid 00

01A10/AP Valid 0

0A11 Valid 0

0A12/BC#

Valid

0A[15:13] Valid 0

MOD

Notes:

1. READ with BL8 either by MRS or OTF.

2. Memory controller must drive 0 on A[2:0].

8Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

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Rev 2.0 June 2016

Alliance Memory Inc. reserves the right to change products or specification without notice

Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070

TEL: (650) 610-6800 FAX: (650) 620-9211