Datasheet

and
t
RP is met). When the MPR is enabled, any subsequent READ or RDAP commands
are redirected to the multipurpose register. The resulting operation when either a READ
or a RDAP command is issued, is defined by MR3[1:0] when the MPR is enabled (see
Table 75 (page 143)). When the MPR is enabled, only READ or RDAP commands are al-
lowed until a subsequent MRS command is issued with the MPR disabled (MR3[2] = 0).
Power-down mode, self refresh, and any other nonREAD/RDAP commands are not al-
lowed during MPR enable mode. The RESET function is supported during MPR enable
mode.
Figure 57: Multipurpose Register (MPR) Block Diagram
Memory core
MR3[2] = 0 (MPR off)
DQ, DM, DQS, DQS#
Multipurpose register
predefined data for READs
MR3[2] = 1 (MPR on)
Notes:
1. A predefined data pattern can be read out of the MPR with an external READ com-
mand.
2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When
the data flow is defined, the MPR contents can be read out continuously with a regular
READ or RDAP command.
Table 74: MPR Functional Description of MR3 Bits
MR3[2] MR3[1:0]
FunctionMPR MPR READ Function
0 “Don’t Care” Normal operation, no MPR transaction
All subsequent READs come from the DRAM memory array
All subsequent WRITEs go to the DRAM memory array
1 A[1:0]
(see Table 75 (page 143))
Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and
2
MPR Functional Description
The MPR JEDEC definition enables either a prime DQ (DQ0 on a x4 and a x8; on a x16,
DQ0 = lower byte and DQ8 = upper byte) to output the MPR data with the remaining
DQs driven LOW, or for all DQs to output the MPR data . The MPR readout supports
fixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READ
latencies and AC timings applicable, provided the DLL is locked as required.
8Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 3 (MR3)
142
Rev 2.0 June 2016
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