Datasheet

quired to program the correct value of write recovery, which is calculated by dividing
t
WR (ns) by
t
CK (ns) and rounding up a noninteger value to the next integer:
WR (cycles) = roundup (
t
WR (ns)/
t
CK (ns)).
Precharge Power-Down (Precharge PD)
The precharge power-down (precharge PD) bit applies only when precharge power-
down mode is being used. When MR0[12] is set to 0, the DLL is off during precharge
power-down, providing a lower standby current mode; however,
t
XPDLL must be satis-
fied when exiting. When MR0[12] is set to 1, the DLL continues to run during precharge
power-down mode to enable a faster exit of precharge power-down mode; however,
t
XP
must be satisfied when exiting (see Power-Down Mode (page 177)).
CAS Latency (CL)
CAS latency (CL) is defined by MR0[6:4], as shown in Figure 50 (page 132). CAS latency
is the delay, in clock cycles, between the internal READ command and the availability of
the first bit of output data. CL can be set to 5 through 14. DDR3 SDRAM do not support
half-clock latencies.
Examples of CL = 6 and CL = 8 are shown below. If an internal READ command is regis-
tered at clock edge n, and the CAS latency is m clocks, the data will be available nomi-
nally coincident with clock edge n + m. See Speed Bin Tables for the CLs supported at
various operating frequencies.
Figure 51: READ Latency
READ NOP NOP NOP NOP NOP NOPNOP
CK
CK#
Command
DQ
DQS, DQS#
DQS, DQS#
T0 T1 T2 T3 T4 T5 T6 T7 T8
Don’t Care
CK
CK#
Command
DQ
READ NOP NOP NOP NOP NOP NOPNOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
DI
n + 3
DI
n + 1
DI
n + 2
DI
n + 4
DI
n
DI
n
NOP
NOP
AL = 0, CL = 8
AL = 0, CL = 6
Transitioning Data
Notes:
1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible.
2. Shown with nominal
t
DQSCK and nominal
t
DSDQ.
8Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 0 (MR0)
134
Rev 2.0 June 2016
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