Datasheet

Mode Registers
Mode registers (MR0–MR3) are used to define various modes of programmable opera-
tions of the DDR3 SDRAM. A mode register is programmed via the mode register set
(MRS) command during initialization, and it retains the stored information (except for
MR0[8], which is self-clearing) until it is reprogrammed, RESET# goes LOW, the device
loses power.
Contents of a mode register can be altered by re-executing the MRS command. Even if
the user wants to modify only a subset of the mode register’s variables, all variables
must be programmed when the MRS command is issued. Reprogramming the mode
register will not alter the contents of the memory array, provided it is performed cor-
rectly.
The MRS command can only be issued (or re-issued) when all banks are idle and in the
precharged state (
t
RP is satisfied and no data bursts are in progress). After an MRS com-
mand has been issued, two parameters must be satisfied:
t
MRD and
t
MOD. The control-
ler must wait
t
MRD before initiating any subsequent MRS commands.
Figure 48: MRS to MRS Command Timing (
t
MRD)
Valid Valid
MRS
1
MRS
2
NOP NOP NOP NOP
T0 T1 T2 Ta0 Ta1 Ta2
CK#
CK
Command
Address
CKE
3
Don’t Care
Indicates break
in time scale
t
MRD
Notes:
1. Prior to issuing the MRS command, all banks must be idle and precharged,
t
RP (MIN)
must be satisfied, and no data bursts can be in progress.
2.
t
MRD specifies the MRS to MRS command minimum cycle time.
3. CKE must be registered HIGH from the MRS command until
t
MRSPDEN (MIN) (see Pow-
er-Down Mode (page 177)).
4. For a CAS latency change,
t
XPDLL timing must be met before any non-MRS command.
The controller must also wait
t
MOD before initiating any non-MRS commands (exclud-
ing NOP and DES). The DRAM requires
t
MOD in order to update the requested features,
with the exception of DLL RESET, which requires additional time. Until
t
MOD has been
satisfied, the updated features are to be assumed unavailable.
8Gb: x4, x8, x16 DDR3L SDRAM
Mode Registers
130
Rev 2.0 June 2016
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