Datasheet

Write Leveling Mode Exit Procedure
After the DRAM are leveled, they must exit from write leveling mode before the normal
mode can be used. Figure 45 depicts a general procedure for exiting write leveling
mode. After the last rising DQS (capturing a 1 at T0), the memory controller should stop
driving the DQS signals after
t
WLO (MAX) delay plus enough delay to enable the memo-
ry controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls become
undefined when DQS no longer remains LOW, and they remain undefined until
t
MOD
after the MRS command (at Te1).
The ODT input should be de-asserted LOW such that ODTLoff (MIN) expires after the
DQS is no longer driving LOW. When ODT LOW satisfies
t
IS, ODT must be kept LOW (at
~Tb0) until the DRAM is ready for either another rank to be leveled or until the normal
mode can be used. After DQS termination is switched off, write level mode should be
disabled via the MRS command (at Tc2). After
t
MOD is satisfied (at Te1), any valid com-
mand may be registered by the DRAM. Some MRS commands may be issued after
t
MRD
(at Td1).
Figure 45: Write Leveling Exit Procedure
NOP
CK
T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Tc2 Td0 Td1 Te0 Te1
CK#
Command
ODT
R
TT(DQ)
NOPNOP NOP NOP NOP NOP MRS NOP NOP
Address
MR1
Valid Valid
Valid
Valid
Don’t CareTransitioning
R
TT
DQS, R
TT
DQS#
R
TT,nom
Undefined Driving Mode
t
AOF (MAX)
t
MRD
Indicates break
in time scale
DQS, DQS#
CK = 1
DQ
t
IS
t
AOF (MIN)
t
MOD
t
WLO +
t
WLOE
ODTLoff
Note:
1. The DQ result, = 1, between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing
CK HIGH just after the T0 state.
8Gb: x4, x8, x16 DDR3L SDRAM
Write Leveling
125
Rev 2.0 June 2016
© 2015 Alliance Memory, Inc. All rights reserved.
Alliance Memory Inc. reserves the right to change products or specification without notice
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070
TEL: [phone] FAX: [phone]