Datasheet

Figure 44: Write Leveling Sequence
CK
CK#
Command
T1 T2
Early remaining DQ
Late remaining DQ
t
WLOE
NOP
2
NOP
MRS
1
NOP NOP NOP NOP NOP NOP NOP NOP NOP
t
WLS
t
WLH
Don’t CareUndefined Driving Mode
Indicates break
in time scale
Prime DQ
5
Differential DQS
4
ODT
t
MOD
t
DQSL
3
t
DQSL
3
t
DQSH
3
t
DQSH
3
t
WLO
t
WLMRD
t
WLDQSEN
t
WLO
t
WLO
t
WLO
Notes:
1. MRS: Load MR1 to enter write leveling mode.
2. NOP: NOP or DES.
3. DQS, DQS# needs to fulfill minimum pulse width requirements
t
DQSH (MIN) and
t
DQSL
(MIN) as defined for regular writes. The maximum pulse width is system-dependent.
4. Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are
the zero crossings. The solid line represents DQS; the dotted line represents DQS#.
5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ
are driven LOW and remain in this state throughout the leveling procedure.
8Gb: x4, x8, x16 DDR3L SDRAM
Write Leveling
124
Rev 2.0 June 2016
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