Datasheet

Figure 42: Change Frequency During Precharge Power-Down
CK
CK#
Command
NOPNOPNOP
Address
CKE
DQ
DM
DQS, DQS#
NOP
t
CK
Enter precharge
power-down mode
Exit precharge
power-down mode
T0 T1 Ta0 Tc0Tb0T2
Don’t Care
t
CKE
t
XP
MRS
DLL RESET
Valid
Valid
NOP
t
CH
t
IH
t
IS
t
CL
Tc1 Td0 Te1Td1
t
CKSRE
t
CH
b
t
CL
b
t
CK
b
t
CH
b
t
CL
b
t
CK
b
t
CH
b
t
CL
b
t
CK
b
t
CPDED
ODT
NOP
Te0
Previous clock frequency New clock frequency
Frequency
change
Indicates break
in time scale
t
IH
t
IS
t
IH
t
IS
t
DLLK
t
AOFPD/
t
AOF
t
CKSRX
High-Z
High-Z
Notes:
1. Applicable for both SLOW-EXIT and FAST-EXIT precharge power-down modes.
2.
t
AOFPD and
t
AOF must be satisfied and outputs High-Z prior to T1 (see On-Die Termina-
tion (ODT) for exact requirements).
3. If the R
TT,nom
feature was enabled in the mode register prior to entering precharge
power-down mode, the ODT signal must be continuously registered LOW, ensuring R
TT
is in an off state. If the R
TT,nom
feature was disabled in the mode register prior to enter-
ing precharge power-down mode, R
TT
will remain in the off state. The ODT signal can
be registered LOW or HIGH in this case.
8Gb: x4, x8, x16 DDR3L SDRAM
Input Clock Frequency Change
120
Rev 2.0 June 2016
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