Datasheet

Input Clock Frequency Change
When the DDR3 SDRAM is initialized, the clock must be stable during most normal
states of operation. This means that after the clock frequency has been set to the stable
state, the clock period is not allowed to deviate, except for what is allowed by the clock
jitter and spread spectrum clocking (SSC) specifications.
The input clock frequency can be changed from one stable clock rate to another under
two conditions: self refresh mode and precharge power-down mode. It is illegal to
change the clock frequency outside of those two modes. For the self refresh mode con-
dition, when the DDR3 SDRAM has been successfully placed into self refresh mode and
t
CKSRE has been satisfied, the state of the clock becomes a “Don’t Care.” When the
clock becomes a “Don’t Care,” changing the clock frequency is permissible if the new
clock frequency is stable prior to
t
CKSRX. When entering and exiting self refresh mode
for the sole purpose of changing the clock frequency, the self refresh entry and exit
specifications must still be met.
The precharge power-down mode condition is when the DDR3 SDRAM is in precharge
power-down mode (either fast exit mode or slow exit mode). Either ODT must be at a
logic LOW or R
TT,nom
and R
TT(WR)
must be disabled via MR1 and MR2. This ensures
R
TT,nom
and R
TT(WR)
are in an off state prior to entering precharge power-down mode,
and CKE must be at a logic LOW. A minimum of
t
CKSRE must occur after CKE goes LOW
before the clock frequency can change. The DDR3 SDRAM input clock frequency is al-
lowed to change only within the minimum and maximum operating frequency speci-
fied for the particular speed grade (
t
CK [AVG] MIN to
t
CK [AVG] MAX). During the input
clock frequency change, CKE must be held at a stable LOW level. When the input clock
frequency is changed, a stable clock must be provided to the DRAM
t
CKSRX before pre-
charge power-down may be exited. After precharge power-down is exited and
t
XP has
been satisfied, the DLL must be reset via the MRS. Depending on the new clock fre-
quency, additional MRS commands may need to be issued. During the DLL lock time,
R
TT,nom
and R
TT(WR)
must remain in an off state. After the DLL lock time, the DRAM is
ready to operate with a new clock frequency.
8Gb: x4, x8, x16 DDR3L SDRAM
Input Clock Frequency Change
119
Rev 2.0 June 2016
© 2015 Alliance Memory, Inc. All rights reserved.
Alliance Memory Inc. reserves the right to change products or specification without notice
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070
TEL: [phone] FAX: [phone]