Datasheet

Figure 39: DLL Enable Mode to DLL Disable Mode
Command
T0 T1 Ta0 Ta1 Tb0 Tc0 Td0 Td1 Te0 Te1 Tf0
CK
CK#
ODT
9
Valid
1
Don’t Care
Valid
1
SRE
3
NOP
MRS
2
NOP
SRX
4
MRS
5
Valid
1
NOP NOP
Indicates break
in time scale
t
MOD
t
CKSRE
t
MOD
t
XS
t
CKESR
CKE
t
CKSRX
876
Notes:
1. Any valid command.
2. Disable DLL by setting MR1[0] to 1.
3. Enter SELF REFRESH.
4. Exit SELF REFRESH.
5. Update the mode registers with the DLL disable parameters setting.
6. Starting with the idle state, R
TT
is in the High-Z state.
7. Change frequency.
8. Clock must be stable
t
CKSRX.
9. Static LOW in the case that R
TT,nom
or R
TT(WR)
is enabled; otherwise, static LOW or HIGH.
A similar procedure is required for switching from the DLL disable mode back to the
DLL enable mode. This also requires changing the frequency during self refresh mode
(see Figure 40 (page 117)).
1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT
is turned off, and R
TT,nom
and R
TT(WR)
are High-Z), enter self refresh mode.
2. After
t
CKSRE is satisfied, change the frequency to the new clock rate.
3. Self refresh may be exited when the clock is stable with the new frequency for
t
CKSRX. After
t
XS is satisfied, update the mode registers with the appropriate val-
ues. At a minimum, set MR1[0] to 0 to enable the DLL. Wait
t
MRD, then set MR0[8]
to 1 to enable DLL RESET.
4. After another
t
MRD delay is satisfied, update the remaining mode registers with
the appropriate values.
5. The DRAM will be ready for its next command in the DLL enable mode after the
greater of
t
MRD or
t
MOD has been satisfied. However, before applying any com-
mand or function requiring a locked DLL, a delay of
t
DLLK after DLL RESET must
be satisfied. A ZQCL command should be issued with the appropriate timings met.
8Gb: x4, x8, x16 DDR3L SDRAM
Commands
116
Rev 2.0 June 2016
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