Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
Figure 38: Refresh Mode
NOP
1
NOP
1
NOP
1
PRE
RA
Bank(s)
3
BA
REF NOP
5
REF
2
NOP
5
ACTNOP
5
One bank
All banks
t
CK
t
CH
t
CL
RA
t
RFC
2t
RP
t
RFC (MIN)
T0
T1
T2 T3
T4
Ta0
Tb0
Ta1
Tb1 Tb2
Don’t Care
Indicates break
in time scale
Valid
5
Valid
5
Valid
5
CK
CK#
Command
CKE
Address
A10
BA[2:0]
DQ
4
DM
4
DQS, DQS#
4
Notes:
1. NOP commands are shown for ease of illustration; other valid commands may be possi-
ble at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH
commands, but may be inactive at other times (see Power-Down Mode (page 177)).
2. The second REFRESH is not required, but two back-to-back REFRESH commands are
shown.
3. “Don’t Care” if A10 is HIGH at this point; however, A10 must be HIGH if more than one
bank is active (must precharge all active banks).
4. For operations shown, DM, DQ, and DQS signals are all “Don’t Care”/High-Z.
5. Only NOP and DES commands are allowed after a REFRESH command and until
t
RFC
(MIN) is satisfied.
SELF REFRESH
The SELF REFRESH command is used to retain data in the DRAM, even if the rest of the
system is powered down. When in self refresh mode, the DRAM retains data without ex-
ternal clocking. Self refresh mode is also a convenient method used to enable/disable
the DLL as well as to change the clock frequency within the allowed synchronous oper-
ating range (see Input Clock Frequency Change (page 119)). All power supply inputs
(including V
REFCA
and V
REFDQ
) must be maintained at valid levels upon entry/exit and
during self refresh mode operation. V
REFDQ
may float or not drive V
DDQ
/2 while in self
refresh mode under the following conditions:
•V
SS
< V
REFDQ
< V
DD
is maintained
•V
REFDQ
is valid and stable prior to CKE going back HIGH
• The first WRITE operation may not occur earlier than 512 clocks after V
REFDQ
is valid
• All other self refresh mode exit timing requirements are met
8Gb: x4, x8, x16 DDR3L SDRAM
Commands
114
Rev 2.0 June 2016
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