Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
Figure 33: Tangent Line for
t
IH (Command and Address – Clock)
V
SS
Hold slew rate
falling signal
=
V
DDQ
V
IH(AC)min
V
IH(DC)min
V
REF(DC)
V
IL(DC)max
V
IL(AC)max
Tangen t
line
DC to V
REF
region
Hold slew rate
rising signal
=
DQS
DQS#
CK#
CK
t
IS
t
IH
t
IS
t
IH
DC to V
REF
region
Tangen t
line
Nominal
line
Nominal
line
Tangent line (V
REF(DC)
- V
IL(DC)max
)
Tangent line (V
IH(DC)min
- V
REF(DC)
)
ΔTR ΔTR
ΔTR
ΔTF
Note:
1. The clock and the strobe are drawn on different time scales.
8Gb: x4, x8, x16 DDR3L SDRAM
Command and Address Setup, Hold, and Derating
99
Rev 2.0 June 2016
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