Datasheet

List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Addressing ......................................................................................................................................... 2
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions .............................................................................................. 18
Table 4: 96-Ball FBGA – x16 Ball Descriptions ................................................................................................. 20
Table 5: Absolute Maximum Ratings .............................................................................................................. 24
Table 6: DDR3L Input/Output Capacitance .................................................................................................... 25
Table 7: Thermal Characteristics .................................................................................................................... 26
Table 8: Timing Parameters Used for I
DD
Measurements – Clock Units ............................................................ 27
Table 9: I
DD0
Measurement Loop ................................................................................................................... 28
Table 10: I
DD1
Measurement Loop .................................................................................................................. 29
Table 11: I
DD
Measurement Conditions for Power-Down Currents ................................................................... 30
Table 12: I
DD2N
and I
DD3N
Measurement Loop ................................................................................................ 31
Table 13: I
DD2NT
Measurement Loop .............................................................................................................. 31
Table 14: I
DD4R
Measurement Loop ................................................................................................................ 32
Table 15: I
DD4W
Measurement Loop ............................................................................................................... 33
Table 16: I
DD5B
Measurement Loop ................................................................................................................ 34
Table 17: I
DD
Measurement Conditions for I
DD6
, I
DD6ET
, and I
DD8
.................................................................... 35
Table 18: I
DD7
Measurement Loop .................................................................................................................. 36
Table 19: I
DD
Maximum Limits Die Rev A ....................................................................................................... 38
Table 20: DDR3L 1.35V DC Electrical Characteristics and Operating Conditions .............................................. 39
Table 21: DDR3L 1.35V DC Electrical Characteristics and Input Conditions ..................................................... 40
Table 22: DDR3L 1.35V Input Switching Conditions – Command and Address ................................................. 41
Table 23: DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#) .............................. 42
Table 24: DDR3L Control and Address Pins ..................................................................................................... 44
Table 25: DDR3L 1.35V Clock, Data, Strobe, and Mask Pins ............................................................................. 44
Table 26: DDR3L 1.35V – Minimum Required Time
t
DVAC for CK/CK#, DQS/DQS# Differential for AC Ringback ... 46
Table 27: Single-Ended Input Slew Rate Definition .......................................................................................... 47
Table 28: DDR3L 1.35V Differential Input Slew Rate Definition ........................................................................ 49
Table 29: On-Die Termination DC Electrical Characteristics ............................................................................ 50
Table 30: 1.35V R
TT
Effective Impedance ........................................................................................................ 51
Table 31: ODT Sensitivity Definition .............................................................................................................. 52
Table 32: ODT Temperature and Voltage Sensitivity ........................................................................................ 52
Table 33: ODT Timing Definitions .................................................................................................................. 53
Table 34: DDR3L(1.35V) Reference Settings for ODT Timing Measurements .................................................... 53
Table 35: DDR3L 34 Ohm Driver Impedance Characteristics ........................................................................... 57
Table 36: DDR3L 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations ........................................... 58
Table 37: DDR3L 34 Ohm Driver I
OH
/I
OL
Characteristics: V
DD
= V
DDQ
= DDR3L@1.35V ..................................... 58
Table 38: DDR3L 34 Ohm Driver I
OH
/I
OL
Characteristics: V
DD
= V
DDQ
= DDR3L@1.45V ..................................... 58
Table 39: DDR3L 34 Ohm Driver I
OH
/I
OL
Characteristics: V
DD
= V
DDQ
= DDR3L@1.283 ..................................... 59
Table 40: DDR3L 34 Ohm Output Driver Sensitivity Definition ........................................................................ 59
Table 41: DDR3L 34 Ohm Output Driver Voltage and Temperature Sensitivity .................................................. 59
Table 42: DDR3L 40 Ohm Driver Impedance Characteristics ........................................................................... 60
Table 43: DDR3L 40 Ohm Output Driver Sensitivity Definition ........................................................................ 60
Table 44: 40 Ohm Output Driver Voltage and Temperature Sensitivity .............................................................. 61
Table 45: DDR3L Single-Ended Output Driver Characteristics ......................................................................... 62
Table 46: DDR3L Differential Output Driver Characteristics ............................................................................ 63
Table 47: DDR3L Differential Output Driver Characteristics V
OX(AC)
................................................................. 64
Table 48: Single-Ended Output Slew Rate Definition ....................................................................................... 65
Table 49: Differential Output Slew Rate Definition .......................................................................................... 67
Table 50: DDR3L-1066 Speed Bins .................................................................................................................. 68
8Gb: x4, x8, x16 DDR3L SDRAM
Description
9
Rev 2.0 June 2016
© 2015 Alliance Memory, Inc. All rights reserved.
Alliance Memory Inc. reserves the right to change products or specification without notice
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