Datasheet

Figure 37. Full Page Write Cycle
(Burst Length=Full Page)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9
T10
T11 T12 T13 T14 T15 T16 T17 T18
T19 T20 T21 T22
Write
Command
Bank A
RAx
RAx
DAx+1
RBx
CAx RBx
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DBx
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank B
CBx
Burst Stop
Command
DBx+3DBx+1 DBx+2 DBx+4
The burst counter wraps
from the highest order
page address back to zero
during this time interval
RBy
RBy
DBx+5
CLK
CS#
CKE
WE#
A10
DQ
High
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
Activate
Command
Bank B
RAS#
CAS#
BA0,1
A0-A9,
A11
DQM
Data is ignored
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Confidential
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Rev.1.0 Sep.2015