Datasheet

Figure 36. Full Page Read Cycle
(Burst Length=Full Page, CAS# Latency=3)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9
T10
T11 T12 T13 T14 T15 T16 T17 T18
T19 T20 T21 T22
Read
Command
Bank A
RAx
RAx
Ax+1
RBx
CAx RBx
Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Bx
Activate
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank B
CBx
Burst Stop
Command
Bx+3Bx+1 Bx+2 Bx+4
The burst counter wraps
from the highest order
page address back to zero
during this time interval
t
RP
RBy
RBy
Bx+5
CLK
CS#
CKE
WE#
A10
DQ
High
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
Activate
Command
Bank B
RAS#
CAS#
BA0,1
A0-A9,
A11
DQM
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Confidential
-39/47-
Rev.1.0 Sep.2015