Datasheet

Figure 33. Interleaved Column Write Cycle
(Burst Length=4)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9
T10
T11 T12 T13 T14 T15 T16 T17 T18
T19 T20 T21 T22
Write
Command
Bank A
RAx
RAx
RBw
DAx0 DAx1 DBy0
Write
Command
Bank B
CLK
RBw
CAx CBw
DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy1
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
CS#
CKE
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
CBx CBy CAy
t
RCD
Write
Command
Bank B
Write
Command
Bank A
DBz0DAy0 DAy1 DBz1
Write
Command
Bank B
CBz
t
RRD
>t
RRD (min)
t
WR
t
WR
DBz2 DBz3
Precharge
Command
Bank B
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Confidential
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Rev.1.0 Sep.2015