Datasheet

Figure 31. Read and Write Cycle
(Burst Length=4, CAS# Latency=3)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9
T10
T11 T12 T13 T14 T15 T16 T17 T18
T19 T20 T21 T22
Read
Command
Bank A
RAx
RAx
DAy1
CLK
CAx CAz
Ax0 Ax1 Ax2 Ax3 DAy0
Write
Command
Bank A
The Write Data
is Masked with a
Zero Clock
Latency
Read
Command
Bank A
The Read Data
is Masked with a
Two Clock
Latency
CS#
CKE
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
Az1 Az3
CAy
DAy3 Az0
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Confidential
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Rev.1.0 Sep.2015