Datasheet

Figure 23. Self Refresh Entry & Exit Cycle
CLK
CS#
T0
T1 T2
CKE
Don’t Care
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
Self Refresh Entry
T3 T4 T5 T6 T7 T8 T9
T10
T11 T12 T13 T14 T15 T16 T17 T18 T19
Self Refresh Exit Auto Refresh
t
IS
Hi-Z
t
IS
t
IH
*Note 1
*Note 2
*Note 3,4
t
PDE
*Note 5
*Note 6
*Note 7
t
XSR
*Note 8
Hi-Z
*Note 9
Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
4. Once the device enters SelfRefresh mode, minimum t
RAS
is required before exit from SelfRefresh.
To Exit SelfRefresh Mode
5. System clock restart and be stable before returning CKE high.
6. Enable CKE and CKE should be set high for valid setup time and hold time.
7. CS# starts from high.
8. Minimum t
XSR
is required after CKE going high to complete SelfRefresh exit.
9. 4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
system uses burst refresh.
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Confidential
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Rev.1.0 Sep.2015