Datasheet

Table 4. Mode Register Bitmap
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0
W.B.L
TM
CAS Latency
BT
Burst Length
A9
Write Burst Length
A8
A7
Test Mode
A3
Burst Type
0
Burst
0
0
Normal
0
Sequential
1
Single Bit
1
0
Reserved
1
Interleave
0
1
Reserved
A6
A5
A4
CAS Latency
A2
A1
A0
Burst Length
0
0
0
Reserved
0
0
0
1
0
0
1
Reserved
0
0
1
2
0
1
0
2 clocks
0
1
0
4
0
1
1
3 clocks
0
1
1
8
1
0
0
Reserved
1
1
1
Full Page (Sequential)
All other Reserved
All other Reserved
Note: Column address is repeated until terminated in Full Page Mode
Figure 15. Mode Register Set Cycle
CLK
CS#
T0
T1 T2 T3 T4 T5 T6 T7
CKE
Don’t Care
RAS#
t
MRD
CAS#
T8 T9 T10
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
t
RP
PrechargeAll
Mode Register
Set Command
Any
Command
Hi-Z
Address Key
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Confidential
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Rev.1.0 Sep.2015