Datasheet

Figure 13. Write to Precharge
Don’t Care
CLK
T0 T1
ADDRESS
T2 T3 T4 T5
COMMAND
tRP
DQM
DQ
tWR
WRITE
Precharge
NOP NOP
Activate
NOP
BANK
COL n
BANK(S) ROW
DIN
N
DIN
N+1
NOP NOP
T6 T7
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
7 Write and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "L", BA = Bank, A10 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the
write operation. Once this command is given, any subsequent command can not occur within a time
delay of {(burst length -1) + t
WR
+ t
RP
(min.)}. At full-page burst, only the write operation is performed
in this command and the auto precharge function is ignored.
Figure 14. Burst Write with Auto-Precharge
(Burst Length = 2)
CLK
DQ
T0
T1 T2 T3 T4 T5 T6
DIN A
0
DIN A
1
T7 T8
COMMAND
Bank A
Activate
NOP NOP
WRITE A
Auto Precharge
NOP NOP NOP NOP NOP
T9
Bank A
Activate
t
DAL
=t
WR
+t
RP
t
DAL
Begin AutoPrecharge
Bank can be reactivated at
completion of t
DAL
8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The
Mode Register Set command programs the values of CAS latency, Addressing Mode and Burst
Length in the Mode register to make SDRAM useful for a variety of different applications. The default
values of the Mode Register after power-up are undefined; therefore this command must be issued
at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to
the mode register. Two clock cycles are required to complete the write in the mode register (refer to
the following figure). The contents of the mode register can be changed using the same command
and the clock cycle requirements during operation as long as all banks are in the idle state.
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Confidential
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Rev.1.0 Sep.2015