Datasheet

Figure 11. Write Interrupted by a Write
(Burst Length = 4)
CLK
T0 T1
COMMAND
T2 T3 T4 T5 T6 T7 T8
DQ
NOP
WRITE A WRITE B
NOP NOP NOP NOP NOP NOP
DIN A
0
DIN B
0
DIN B
1
DIN B
2
DIN B
3
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid
data contention, input data must be removed from the DQs at least one clock cycle before the first
read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
Figure 12. Write Interrupted by a Read
(Burst Length = 4, CAS# Latency = 2, 3)
Don’t Care
CLK
T0 T1
COMMAND
T2 T3 T4 T5 T6 T7 T8
CAS# latency=2
t
CK2,
DQ
CAS# latency=3
t
CK3,
DQ
Input data must be removed from the DQ at least one clock cycle before
the Read data appears on the outputs to avoid data contention
NOP
WRITE A
READ B
NOP NOP
NOP
NOP NOP NOP
DIN A
0
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
DOUT B
3
DOUT B
2
DOUT B
1
DOUT B
0
DIN A
0
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals t
WR
/t
CK
rounded up to the next whole number. In addition, the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Confidential
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Rev.1.0 Sep.2015