Datasheet

Figure 9. Read to Precharge
(CAS# Latency = 2, 3)
CLK
T0 T1
ADDRESS
T2 T3 T4 T5 T6 T7 T8
CAS# latency=2
t
CK2,
DQ
CAS# latency=3
t
CK3,
DQ
COMMAND
tRP
NOPNOP
Precharge
NOP
Bank(s)
NOPNOPREAD A
Bank,
Col A
DOUT A
0
DOUT A
1
DOUT A
3
DOUT A
2
DOUT A
2
DOUT A
1
DOUT A
0
DOUT A
3
Bank
Row
Activate
NOP
Don’t Care
5 Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", BA = Bank, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after the
read operation. Once this command is given, any subsequent command cannot occur within a time
delay of {t
RP
(min.) + burst length}. At full-page burst, only the read operation is performed in this
command and the auto precharge function is ignored.
6 Write command
(RAS# = "H", CAS# = "L", WE# = "L", BA = Bank, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least t
RCD
(min.) before the Write command is
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
Figure 10. Burst Write Operation
(Burst Length = 4)
CLK
DQ
T0
T1 T2 T3 T4 T5 T6
DIN A
0
DIN A
1
DIN A
2
DIN A
3
T7 T8
COMMAND
NOP WRITE A NOP NOP NOP NOP NOP NOP NOP
The first data element and the write
are registered on the same clock edge
Don’t Care
A write burst without the AutoPrecharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Confidential
-11/47-
Rev.1.0 Sep.2015