Datasheet

Figure 6. Read to Write Interval
(Burst Length ≥ 4, CAS# Latency = 2)
CLK
COMMAND
T0
T1
DQM
T2 T3 T4 T5 T6 T7 T8
CAS# latency=2
t
CK2,
DQ
Must be Hi-Z before
the Write Command
NOP NOP
BANKA
ACTIVATE
NOP READ A
WRITE
A
DIN A
0
DIN A
1
NOP NOP
DIN A
2
NOP
T9
DIN A
3
NOP
Figure 7. Read to Write Interval
(Burst Length ≥ 4, CAS# Latency = 2)
Don’t Care
CLK
COMMAND
T0
T1
DQM
T2 T3 T4 T5 T6 T7 T8
CAS# latency=2
t
CK2,
DQ
Must be Hi-Z before
the Write Command
NOPREAD ANOPNOP NOP
DIN B
3
DIN B
2
DIN B
1
DIN B
0
NOP
WRITE B
NOP NOP
Figure 8. Read to Write Interval
(Burst Length
≧
4, CAS# Latency = 3)
CLK
COMMAND
T0
T1 T2 T3 T4 T5 T6
NOP READ A NOP NOP NOP NOP WRITE B NOP
T7 T8
NOP
DQM
DOUT A
0
DIN B
0
DIN B
1
DIN B
2
CAS# Latency=3
t
CK3
, DQ
Must be Hi-Z before
the Write Command
Don’t Care
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS latency.
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Confidential
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Rev.1.0 Sep.2015