Datasheet

ManualsBrandsAlliance Memory ManualsDRAMDRAM 128MB 5.4ns TSOP-II

Revision History

4M x 32bit -AS4C4M32SA - 86-pin TSOP II PACKAGE

Revision Details Date

Rev 1.0 Preliminary datasheet Sep. 2015

AS4C4M32SA-6TIN

AS4C4M32SA-6TCN

AS4C4M32SA-7TCN

Confidential

-1/47-

Rev.1.0 Sep.2015

Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211

Alliance Memory Inc. reserves the right to change products or specification without notice

Summary of content (47 pages)

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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Revision History 4M x 32bit -AS4C4M32SA - 86-pin TSOP II PACKAGE Revision Rev 1.0 Details Preliminary datasheet Date Sep. 2015 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential -1/47- Rev.1.0 Sep.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Overview Features • Fast access time from clock: 5.4/5.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 1.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN CLOCK BUFFER Column Decoder CKE A10/AP DQ0 DQ Buffer COMMAND DECODER DQ31 CONTROL SIGNAL GENERATOR DQM0~3 Row Decoder CS# RAS# CAS# WE# 4096 x 256 x 32 CELL ARRAY (BANK #0) ~ CLK Row Decoder Figure 2.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Pin Descriptions Table 2. Pin Details Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN NC - VDDQ Supply DQ Power: Provide isolated power to DQs for improved noise immunity. VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. VDD Supply Power Supply: 3.3V ±0.3V. VSS Supply Ground Confidential No Connect: These pins should be left unconnected. -6/47- Rev.1.0 Sep.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 3 shows the truth table for the operation commands. Table 3.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Commands 1 BankActivate (RAS# = "L", CAS# = "H", WE# = "H", BA 0,1= Bank, A0-A11 = Row Address) The BankActivate command activates the idle bank designated by the BA0,1 (Bank Activate) signal. By latching the row address on A0 to A11 at the time of this command, the selected row access is initiated. The read or write operation in the same bank can occur after a time delay of tRCD(min.) from the time of bank activation.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 4. Burst Read Operation (Burst Length = 4, CAS# Latency = 2, 3) T0 T1 READ A NOP T2 T3 T4 T5 T6 T7 T8 CLK COMMAND CAS# latency=2 tCK2, DQ NOP NOP NOP NOP NOP NOP NOP DOUT A0 DOUT A1 DOUT A2 DOUT A3 CAS# latency=3 tCK3, DQ DOUT A0 DOUT A1 DOUT A2 DOUT A3 The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e. DQM latency is two clocks for output buffers).
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 6. Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 2) T1 T0 T2 T3 T4 T5 T6 T7 T9 T8 CLK DQM COMMAND NOP NOP BANKA ACTIVATE NOP CAS# latency=2 tCK2, DQ READ A NOP WRITE A NOP NOP DIN A0 DIN A1 DIN A2 NOP DIN A3 Must be Hi-Z before the Write Command Figure 7.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 9.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 11. Write Interrupted by a Write (Burst Length = 4) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP DQ WRITE A WRITE B NOP NOP NOP DIN A0 DIN B0 DIN B1 DIN B2 DIN B3 NOP NOP NOP The Read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 13. Write to Precharge T0 T1 T2 T3 T4 T5 T6 T7 Activate NOP CLK DQM tRP COMMAND WRITE ADDRESS BANK COL n NOP NOP Precharge NOP NOP BANK(S) ROW tWR DIN N+1 DIN N DQ Don’t Care Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Table 4. Mode Register Bitmap BA1 0 A9 0 1 A6 0 0 0 0 1 BA0 0 A11 0 A10 A9 0 W.B.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN • Burst Definition, Addressing Sequence of Sequential and Interleave Mode Table 5.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 17. Termination of a Burst Write Operation (Burst Length = X) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND DQ NOP WRITE A NOP NOP DIN A0 DIN A1 DIN A2 Burst Stop NOP NOP NOP NOP Don’t Care 11 Device Deselect command (CS# = "H") The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No Operation command.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN 16 Clock Suspend Mode Exit / PowerDown Mode Exit command When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the subsequent cycle by providing this command (asserting CKE "HIGH", the command should be NOP or deselect). When the device is in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active state. tXSR(min.) is required when the device exits from the PowerDown mode.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Table 6. Absolute Maximum Rating Symbol VIN, VOUT Item Input, Output Voltage Values -1.0 ~ 4.6 Unit V VDD, VDDQ Power Supply Voltage -1.0 ~ 4.6 V Commercial 0 ~ 70 °C TA Ambient Temperature Industrial -40 ~ 85 °C TSTG Storage Temperature -55 ~ 150 °C PD Power Dissipation 1.1 W IOS Short Circuit Output Current 50 mA Note Note: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Table 9. D.C. Characteristics (VDD = 3.3V ±0.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Table 10. Electrical Characteristics and Recommended A.C. Operating Conditions (VDD = 3.3V ±0.3V, TA = -40~85°C) (Note: 5~8) Symbol -5 A.C. Parameter -6 -7 Min. Max. Min. Max. Min. Max.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Table 11. LVTTL Interface Reference Level of Output Signals 1.4V / 1.4V Output Load Reference to the Under Output Load (B) Input Signal Levels (VIH /VIL) 2.4V / 0.4V Transition Time (Rise and Fall) of Input Signals 1ns Reference Level of Input Signals 1.4V 1.4V 3.3V 50Ω 1.2KΩ Output Output 30pF Z0=50Ω 870Ω Figure 18.1 LVTTL D.C. Test Load (A) 30pF Figure 18.2 LVTTL A.C. Test Load (B) 7. Transition times are measured between VIH and VIL.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Timing Waveforms Figure 19.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 20.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 21. Auto Refresh (Burst Length=4, CAS# Latency=3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx tRP tRC tRC CAx tRCD DQM DQ Ax0 Precharge All Command Auto Refresh Command Auto Refresh Command Activate Command Bank A Read Command Bank A Don’t Care Confidential -24/47- Rev.1.0 Sep.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 22.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 23. Self Refresh Entry & Exit Cycle T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 CLK *Note 2 CKE tXSR *Note 5 *Note 1 *Note 3,4 *Note 8 tPDE tIS tIH *Note 6 tIS *Note 7 CS# RAS# *Note 9 CAS# WE# BA0,1 A10 A0-A9, A11 DQM DQ Hi-Z Hi-Z Self Refresh Exit Self Refresh Entry Auto Refresh Don’t Care Note: To Enter SelfRefresh Mode 1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle. 2.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 24. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx CAx DQM DQ tHZ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Clock Suspend 1 Cycle Clock Suspend 2 Cycles Ax3 Clock Suspend 3 Cycles Don’t Care Confidential -27/47- Rev.1.0 Sep.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 25. Clock Suspension During Burst Write (Using CKE) (Burst Length=4) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx CAx DQM DQ Hi-Z DAx0 Activate Command Bank A Confidential DAx1 Clock Suspend 1 Cycle Write Command Bank A DAx2 Clock Suspend 2 Cycles DAx3 Clock Suspend 3 Cycles Don’t Care -28/47- Rev.1.0 Sep.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 26.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 27.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 28.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 29.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 30.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 31.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 32.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 33.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 34.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 35.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 36.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 37.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 38.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 39.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 40.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 41.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 42.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN Figure 43. 86 Pin TSOP II Package Outline Drawing Information 86 0.254 HE E 44 θ° L L1 A1 A2 e Symbol A A1 A2 B C D E e HE L L1 S y θ L L1 y B S C 43 D A 1 Dimension in inch Min Normal Max 0.047 －－ 0.002 0.004 0.008 0.035 0.039 0.043 0.007 0.009 0.011 0.005 －－ 0.87 0.875 0.88 0.395 0.400 0.405 0.0197 －－ Min － 0.05 0.9 0.17 － 22.09 10.03 － Dimension in mm Normal － 0.10 1 0.22 0.127 22.22 10.16 0.50 Max 1.20 0.2 1.1 0.27 － 22.35 10.
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AS4C4M32SA-6TIN AS4C4M32SA-6TCN AS4C4M32SA-7TCN PART NUMBERING SYSTEM AS4C DRAM 4M32SA 6/7 128Mb=4Mx32 6=166MHz A die version 7=143MHz T T = TSOP II C/I N C=Commercial (0°C - +70°C) I=Industrial Indicates Pb and Halogen Free (-40°C - +85°C) Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved.