Datasheet

Figure 32.2. Interleaved Column Read Cycle
(Burst Length=4, CAS# Latency=3)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9
T10
T11 T12 T13 T14 T15 T16 T17 T18
T19 T20 T21 T22
Read
Command
Bank A
RAx
RAx
RBx
Ax0 Ax1 Bz0
Precharge
Command
Bank B
CLK
RBx
CAx CBx
Ax2 Ax3 Bx0 Bx1 By0 By1 Bz1
Activate
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank A
CS#
CKE
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
CBy CBz CAy
t
RCD
t
AC
Read
Command
Bank B
Read
Command
Bank A
Ay2Ay0 Ay1 Ay3
Read
Command
Bank B
AS4C4M16SA-C&I
Confidential
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Rev.5.0 October 2018