Datasheet

Figure 32.1. Interleaving Column Read Cycle
(Burst Length=4, CAS# Latency=2)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9
T10
T11 T12 T13 T14 T15 T16 T17 T18
T19 T20 T21 T22
Read
Command
Bank A
RAx
RAx
RBx
Ax0 Ax1 By0
Read
Command
Bank A
CLK
RBx
CAy CBw
Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 By1
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank B
CS#
CKE
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
Bz2 Bz3
CBx CBy CAy CBz
t
RCD
t
AC
Read
Command
Bank B
Read
Command
Bank B
Bz0Ay0 Ay1 Bz1
Precharge
Command
Bank A
AS4C4M16SA-C&I
Confidential
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Rev.5.0 October 2018