Datasheet

Figure 22. Power on Sequence and Auto Refresh
Hi-Z
T0 T1 T2
Don’t Care
Inputs must be
Stable for
200μs
T3 T4 T5 T6 T7 T8 T9
T10
T11 T12 T13 T14 T15 T16 T17 T18
T19 T20 T21 T22
t
MRD
Extended
Mode Register
Set Command
High Level
Is reguired
Minimum for 2 Refresh Cycles are required
t
RP
Precharge All
Command
1st Auto Refresh
(*)
Command
2nd Auto Refresh
(*)
Command
Any
Command
Note
(*)
: The Auto Refresh command can be issue before or after Mode Register Set command
CLK
CS#
CKE
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
Address Key
Mode Register
Set Command
t
MRD
BA0=H
BA1=L
BA0=L
BA1=L
AS4C4M16SA-C&I
Confidential
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Rev.5.0 October 2018