Datasheet

Confidential
64M – (4M x 16 bit) Synchronous DRAM (SDRAM)
Advanced (Rev. 5.0, Oct. /2018)
Features
 Fast access time from clock: 4.5/5.4/5.4 ns

Fast clock rate: 200/166/143 MHz
 Fully synchronous operation
 Internal pipelined architecture
 1M word x 16-bit x 4-bank
 Programmable Mode registers
- CAS Latency: 2 or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential or Interleaved
- Burst stop function
- Optional drive strength control
 Operating temperature range
- Commercial (0 ~ 70°C)
- Industrial (-40 ~ 85°C)
 Auto Refresh and Self Refresh
 4096 refresh cycles/64ms
 CKE power down mode
 Single +3.3V  0.3V power supply
 Interface: LVTTL
 54-pin 400 mil plastic TSOP II package
 54-ball 8.0 x 8.0 x 1.2mm (max) FBGA
package
 60-ball 6.4 x 10.1 x 1.0mm FBGA package
- All parts ROHS Compliant
Overview
The 64Mb SDRAM is a high-speed CMOS
synchronous DRAM containing 64 Mbits. It is internally
configured as 4 Banks of 1M word x 16 DRAM with a
synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Read and
write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of a
Bank Activate command which is then followed by a
Read or Write command.
The SDRAM provides for programmable Read or
Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy
to use. By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth and particularly well suited to high
performance PC applications.
Table 1. Key Specifications
AS4C4M16S
tCK3
Clock Cycle time(min.)
tAC3
Access time from CLK (max.)
tRAS
Row Active time(min.)
tRC
Row Cycle time(min.)
Table 2.Ordering Information
Part Number
Frequency
Package
Temperature
Temp Range
AS4C4M16SA-6BIN
166MHz
54-Ball FBGA
Industrial
-40 ~ 85°C
AS4C4M16SA-7BCN
143MHz
54-Ball FBGA
Commercial
0 ~ 70°C
AS4C4M16SA-6TIN
166MHz
54-Pin TSOPII
Industrial
-40 ~ 85°C
AS4C4M16SA-7TCN
143MHz
54-Pin TSOPII
Commercial
0 ~ 70°C
AS4C4M16SA-6TCN
166MHz
54-Pin TSOPII
Commercial
0 ~ 70°C
B: indicates FBGA package B2: indicates a second FBGA package option
T: indicates TSOP II
package N: indicates Pb and
Halogen Free
AS4C4M16SA-5TCN 200MHz 0 ~ 70°C
AS4C4M16SA-C&I
Confidential
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Rev.5.0 October 2018
-5
-6
-7
Unit
4.5
40
55
5
5.4
42
60
6
5.4
42
63
7
ns
ns
ns
ns
AS4C4M16SA-7B2CN 143MHz 60-Ball FBGA Commercial 0 ~ 70°C
54-Pin TSOPII Commercial