Datasheet

o
ne
tra
n
sition
follow
e
d by the
worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin
skew and output pattern effects, and p-channel to n-channel variation of the output drivers.
12. The only time that the clock frequency is allowed to change is during clock stop, power-down or self-refresh modes.
13. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising input signals, and
VI
H(DC) to VIL(AC) for falling input sig
nals.
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal
transitions through the DC region must be monotonic.
15. Input slew rate ≥ 1.0 V/ns.
16. Input slew rate ≥ 0.5 V/ns and < 1.0 V/ns.
17. These parameters guarantee device timing but they are not necessarily tested on each device.
18. The transition time for address and command inputs is measured between VIH and VIL.
19. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
20.
tDQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers
for
any given cycle.
21. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before the
corresponding CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the
device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If
a
p
revious write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
tDQSS.
22
. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
23
. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in
the system. It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled).
24. At least one clock cycle is required during tWR time when in auto precharge mode.
25. Minimum 3 clocks of tDAL (=tWR + tRP) is required because it need minimum 2 clocks for tWR and minimum 1 clock for
tRP.
tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms above, if not already an integer, round to the next higher integer.
26. There must be at least two clock pulses during the tXSR period.
27. There must be at least one clock pulse during the tXP period.
28.
tREFI values are dependence on density and bus wi
dth.
29. A maximum of 8 Refresh commands can be posted to any given M, meaning that the maximum absolute interval between
any Refresh command and the next Refresh command is 8*tREFI.
CAS Latency Definition (With CL=3)
AS4C32M16MD1A-5BCN
Confidential
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Rev.1.2 July 2016