Datasheet

8.5 AC Timings
8.5.1 AC Timing Table
[Recommended Operating Conditions: Notes 1-29]
PARAMETER SYMBOL
- 5
UNIT NOTES
MIN MAX
DQ output access time
from CK/
CK
CL=3
tAC
2.0 5.0
ns
CL=2 2.0 6.5
DQS output access time from
CK/
CK
CL=3
tDQSCK
2.0 5.0
ns
CL=2 2.0 6.5
Clock high-level width tCH 0.45 0.55
tCK
Clock low-level width tCL 0.45 0.55
tCK
Clock half period tHP
Min
(tCL, tCH)
ns 10,11
Clock cycle time
CL=3
tCK
5
ns 12
CL=2 12
ns 12
DQ and DM input setup
time
fast slew rate
tDS
0.48
ns 13,14,15
slow slew rate 0.58
ns 13,14,16
DQ and DM input hold time
fast slew rate
tDH
0.48
ns 13,14,15
slow slew rate 0.58
ns 13,14,16
DQ and DM input pulse width tDIPW 1.4
ns 17
Address and control input
setup time
fast slew rate
tIS
0.9
ns 15,18
slow slew rate 1.1
ns 16,18
Address and control input
hold time
fast slew rate
tIH
0.9
ns 15,18
slow slew rate 1.1
ns 16,18
Address and control input pulse width tIPW 2.3
ns 17
DQ & DQS low-impedance time from CK/
CK
tLZ 1.0
ns 19
DQ & DQS high-impedance
time from CK/
CK
CL=3
tHZ
5.0
ns 19
CL=2 6.5
DQS-DQ skew tDQSQ 0.4
ns 20
DQ/DQS output hold time from DQS tQH tHP-tQHS
ns 11
Data hold skew factor tQHS 0.5
ns 11
Write command to 1st DQS latching
transition
tDQSS 0.75 1.25
tCK
DQS input high-level width tDQSH 0.4 0.6
tCK
DQS input low-level width tDQSL 0.4 0.6
tCK
DQS falling edge to CK setup time tDSS 0.2
tCK
DQS falling edge hold time from CK tDSH 0.2
tCK
MODE REGISTER SET command period tMRD 2
tCK
Write preamble setup time tWPRES 0
ns 21
Write postamble tWPST 0.4 0.6
tCK 22
Write preamble tWPRE 0.25
tCK
Read preamble
CL = 3
tRPRE
0.9 1.1
tCK 23
CL = 2 0.5 1.1
tCK 23
Read postamble tRPST 0.4 0.6
tCK
ACTIVE to PRECHARGE command period tRAS 40 70,000
ns
ACTIVE to ACTIVE command period tRC
tRAS+
tRP
ns
AUTO REFRESH to ACTIVE/AUTO
REFRESH command period
tRFC 72
ns
AS4C32M16MD1A-5BCN
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Rev.1.2 July 2016