Datasheet

3.1 Signal Descriptions
SIGNAL NAME TYPE DESCRIPTION
CK,/CK Input
Clock: CK and CK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CK
and negative edge of CK. Input and output data is referenced to the
crossing of CK and CK (both directions of crossing). Internal clock
signals are derived from CK/CK.
CKE Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal
clock signals, and device input buffers and output drivers. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), or ACTIVE POWERDOWN (row ACTIVE in
any bank). CKE is synchronous for all functions except for SELF
REFRESH EXIT, which is achieved asynchronously. Input buffers,
excluding CK, CK and CKE, are disabled during power-down and self
refresh mode which are contrived for low standby power consumption.
CS
Input
Chip Select: CS enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS is
registered HIGH. CS provides for external bank selection on systems
with multiple banks. CS is considered part of the command code.
RAS/CAS/WE
Input Command Inputs: RAS, CAS and WE (along with CS) define the
command being entered.
DM, LDM, UDM
Input
Input Data Mask: DM is an input mask signal for w
rite data. Input data is
masked when DM is sampled HIGH along with that input data during a
WRITE access. DM is sampled on both edges of DQS. Although DM
pins are input-only, the DM loading matches the DQ and DQS loading.
LDM corresponds to the data on DQ0-DQ7, UDM corresponds to the
data on DQ8-DQ15.
BA0,BA1
Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
A [n : 0]
Input Address Inputs: provide the row address for ACTIVE commands, and
the column address and AUTO PRECHARGE bit for READ / WRITE
commands, to select one location out of the memory array in the
respective bank. The address inputs also provide the opcode during a
MODE REGISTER SET command.
DQ0-DQ15
I/O
Data Bus: Input / Output
LDQS,UDQS
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned
with read da
ta, centered with write data. Used to capture write data.
LDQS corresponds to the data on DQ0-DQ7, UDQS corresponds to
the data on DQ8-DQ15.
NC
-
No Connect: No internal electrical connection is presen
VDDQ Supply
I/O Power Supply
VSSQ
Supply
I/O Ground
VDD
Supply
Power Supply
VSS
Supply
Ground
Table 3 — Signal Descriptions
AS4C32M16MD1A-5BCN
Confidential
- 4/56 -
Rev.1.2 July 2016