Datasheet

7.8 Auto Precharge
Auto Precharge is a feature which performs the same individual bank precharge function as described above, but without requiring
an explicit command. This is accomplished by using A10 (A10 = High), to enable Auto Precharge in conjunction with a specific
READ or WRITE command. A precharge of the bank / row that is addressed with the READ or WRITE command is automatically
performed upon completion of the read or write burst. Auto Precharge is non persistent in that it is either enabled or disabled for
each individual READ or WRITE command.
Auto Precharge ensures that a precharge is initiated at the earliest valid stage within a burst. The user must not issue another
command to the same bank until the precharging time (t
RP) is completed. This is determined as if an xplicit PRECHARGE
command was issued at the earliest possible time, as described for each burst type in the Operation section of this specification.
7.9 Refresh Requirements
LPDDR SDRAM devices require a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two ways: by
an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode. Dividing the number of device
rows into the rolling 64ms interval defines the average refresh interval (t
REFI), which is a guideline to controllers for distributed
refresh timing.
7.10 Auto Refresh
AUTO REFRESH command (see Figure 33) is used during normal operation of the LPDDR SDRAM. This command is non
persistent, so it must be issued each time a refresh is required.
= Don't Care
(High)
CK
CK
CKE
CS
RAS
CAS
WE
A0-An
BA0,BA1
Figure 33 — Auto Refresh Command
7.11 Self Referesh
The SELF REFRESH command (see Figure 34) can be used to retain data in the LPDDR SDRAM, even if the rest of the system is
powered down. When in the Self Refresh mode, the LPDDR SDRAM retains data without external clocking. The LPDDR SDRAM
device has a built-in timer to accommodate Self Refresh operation. The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is LOW. Input signals except CKE are “Don’t Care” during Self Refresh. The user may halt the
external clock one clock after the SELF REFRESH command is registered.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. The clock is internally disabled
during Self Refresh operation to save power. The minimum time that the device must remain in Self Refresh mode is t
RFC.
The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable prior to CKE going back
High. Once Self Refresh Exit is registered, a delay of at least t
XS must be satisfied before a valid command can be issued to the
device to allow for completion of any internal refresh in progress.
The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for
exit from Self Refresh mode. Upon exit from Self Refresh an extra AUTO REFRESH command is recommended.
Figure 36 shows Self Refresh entry and exit.
In the Self Refresh mode, two additional power-saving options exist: Temperature Compensated Self Refresh (TCSR) and Partial
Array Self Refresh (PASR); they are described in the Extended Mode Register section .
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