Datasheet

7.3 MODE REGISTER
The Mode Register and the Extended Mode Register are loaded via the address inputs. See Mode Register and the Extended
Mode Register descriptions for further details.
The MODE REGISTER SET command (see Figure 8) can only be issued when all banks are idle and no bursts are in progress, and
a subsequent executable command cannot be issued until tMRD (see Figure 9) is met.The values of the mode register and
extended mode register will be retained even when exiting deep power-down.
Figure 8 — Mode Register Set Command
Figure 9 — Mode Register Set Command Timing
7.4. Active
Before any READ or WRITE commands can be issued to a bank in the LPDDR SDRAM, a row in that bank must be opened. This is
accomplished by the ACTIVE command (see Figure 10): BA0 and BA1 select the bank, and the address inputs select the row to be
activated. More than one bank can be active at any time.
Once a row is open, a READ or WRITE command could be issued to that row, subject to the t
RCD specification.
A subsequent ACTIVE command to another row in the same bank can only be issued after the previous row has been closed. The
minimum time interval between two successive ACTIVE commands on the same bank is defined by t
RC.
A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction
of total row-access overhead. The minimum time interval between two successive ACTIVE commands on different banks is defined
by t
RRD. Figure 11 shows the tRCD and tRRD definition.
AS4C32M16MD1A-5BCN
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Rev.1.2 July 2016