Datasheet
1. GENERAL DESCRIPTION
This AS4C32M16MD1A-5BCN is 536,870,912 bits synchronous double data rate Dynamic RAM. Each 134,217,728 bits bank is
organized as 8,192 rows by 1024 columns by 16 bits fabricated with Alliance Memory’s high perfo
rmance CMOS technology. This
device uses
a
double data
rate
architecture
to
achieve hi
gh-
speed operation. The
dou
ble data rate
architectur
e is
essentially a 2n-
prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. Range of operating
frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high
bandwidth and high performance memory system applications.
2. FEATURES
• VDD/VDDQ = 1.7~1.95V
•Data width: x16
•Clock rate: 200MHz
•Partial Array Self-Refresh(PASR)
•Auto Temperature Compensated Self-Refresh(ATCSR)
•Power Down Mode
•Deep Power Down Mode (DPD Mode)
•Programmable output buffer driver strength
•Four internal banks for concurrent operation
•Data mask (DM) for write data
•Clock Stop capability during idle periods
•Auto Pre-charge option for
each burst access
•Double data rate for data output
•Differential clock inputs (CK and CK )
•Bidirectional, data strobe (DQS)
•PKG Type
x16 : 8.0 x 9.0mm 60 Ball FPBGA (Fine Pitch Ball Grid Array)
CAS Latency: 2 and 3
Burst Length: 2, 4, 8 and 16
Burst Type: Sequential or Interleave
64 ms Refresh period
Interface: LVCMOS
Table 1. Speed Grade Information
Speed Grade Clock Frequency CAS Latency
t
RCD
(ns)
t
RP
(ns)
Table 2. Ordering Information
Product part No
Org Temperature
Max Clock (MHz)
AS4C32M16MD1A-5BCN
32Mx 16
Extended -30°C to +85°C
Package
60-ball FPBGA
AS4C32M16MD1A-5BCN
Confidential
- 2/56 -
Rev.1.2 July 2016
200
200MHz
3
15
15
DDR1-400
Operating Temperature Range
Extended (-30°C to +85°C)