Datasheet

Figure 35. Self refresh operation
CK#
CK
CKE
T0 T1 T5 TmT2 T3
CMD
>=t
XSNR
t
RP*
t
CH
t
CL
t
CK
T4 T6 Tn
>=t
XSRD
t
IS
V
IL(ac)
V
IH(ac)
t
IS
NOP
Self
Refresh
ODT
t
AOFD
t
IS
V
IL(ac)
t
IH
t
IS
t
IH
t
IS
t
IH
V
IL(dc)
V
IL(ac)
V
IH(ac)
V
IH(dc)
NOP NOP Valid
NOTE 1 Device must be in the "All banks idle" state prior to entering Self Refresh mode.
NOTE 2 ODT must be turned off t
AOFD
before entering Self Refresh mode, and can be
turned on again when t
XSRD
timing is satisfied.
NOTE 3 t
XSRD
is applied for Read or a Read with autoprecharge command.
t
XSNR
is applied for any command except a Read or a Read with autoprecharge command.
Figure 36. Basic power down entry and exit timing diagram
CK#
CK
Command
CKE
VALID
t
IH
t
CKE min
t
IH
t
IH
t
IH
t
IS
t
IS
t
IS
NOP NOP NOP VALID
VALID
or NOP
t
XP,
t
XARD
t
XARDS
t
CKE(min)
Exit Power-Down mode
Don't Care
Enter Power-Down mode
Figure 37.1.CKE intensive environment
CK#
CKE
t
CKE
NOTE: DRAM guarantees all AC and DC timing & voltage specifications and proper DLL operation with intensive CKE operation
CK
t
CKE
t
CKE
t
CKE
AS4C32M16D2A-25BIN
Alliance Memory Inc.
511 Taylor Way, San Carlos, CA 94070 TEL: [phone] FAX: [phone]
Alliance Memory Inc. reserves the right to change products or specification without notice
Rev.1.2
55
Jun./2014