Datasheet

NOTE 37: t
QH
= t
HP
– t
QHS
, where: t
HP
is the minimum of the absolute half period of the actual input clock; and t
QHS
is
the specification value under the max column. {The less half-pulse width distortion present, the larger the t
QH
value is; and the larger the valid data eye will be.}
NOTE 38: When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
ERR
(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.)
NOTE 39: When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock.)
NOTE 40: When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
JIT
(duty) of the input clock. (output deratings are relative to the SDRAM input clock.)
NOTE 41: When the device is operated with input clock jitter, this parameter needs to be derated by { -
t
JIT
(duty),max - t
ERR
(6-10per),max } and { - t
JIT
(duty),min - t
ERR
(6-10per),min } of the actual input clock. (output
deratings are relative to the SDRAM input clock.)
NOTE 42: For t
AOFD
of DDR2-667/800/1066, the 1/2 clock of t
CK
in the 2.5 x t
CK
assumes a t
CH
(avg), average input
clock HIGH pulse width of 0.5 relative to t
CK
(avg). t
AOF
,min and t
AOF
,max should each be derated by the same
amount as the actual amount of t
CH
(avg) offset present at the DRAM input with respect to 0.5.
NOTE 43: If refresh timing is violated, data corruption may occur and the data must be re-writtern with valid data
before a valid READ can be executed.
AS4C32M16D2A-25BIN
Alliance Memory Inc.
511 Taylor Way, San Carlos, CA 94070 TEL: [phone] FAX: [phone]
Alliance Memory Inc. reserves the right to change products or specification without notice
Rev.1.2
34
Jun./2014