Datasheet

NOTE 9: t
IS
and t
IH
(input setup and hold) derating
For all input signals the total t
IS
(setup time) and t
IH
(hold time) required is calculated by adding the data sheet
t
IS(base)
and t
IH(base)
value to the t
IS
and 
tIH
derating value respectively. Example: t
IS
(total setup time) =
t
IS
(base) + t
IS
For slew rates in between the values listed in Tables 29, the derating values may obtained by linear
interpolation.These values are typically not subject to production test. They are verified by design and
characterization.
Table 29. Derating values for DDR2-667, DDR2-800, DDR2-1066
△tIS and △tIH Derating Values for DDR2-667, DDR2-800, DDR2-1066
CK,CK# Differential Slew Rate
2.0 V/ns 1.5 V/ns 1.0 V/ns
△tIS △tIH △tIS △tIH △tIS △tIH Units Notes
Command/
Address Slew rate
(V/ns)
4.0 +150 +94 +180 +124 +210 +154 ps 1
3.5 +143 +89 +173 +119 +203 +149 ps 1
3.0 +133 +83 +163 +113 +193 +143 ps 1
2.5 +120 +75 +150 +105 +180 +135 ps 1
2.0 +100 +45 +130 +75 +160 +105 ps 1
1.5 +67 +21 +97 +51 +127 +81 ps 1
1.0 0 0 +30 +30 +60 +60 ps 1
0.9 -5 -14 +25 +16 +55 +46 ps 1
0.8 -13 -31 +17 -1 +47 +29 ps 1
0.7 -22 -54 +8 -24 +38 +6 ps 1
0.6 -34 -83 -4 -53 +26 -23 ps 1
0.5 -60 -125 -30 -95 0 -65 ps 1
0.4 -100 -188 -70 -158 -40 -128 ps 1
0.3 -168 -292 -138 -262 -108 -232 ps 1
0.25 -200 -375 -170 -345 -140 -315 ps 1
0.2 -325 -500 -295 -470 -265 -440 ps 1
0.15 -517 -708 -487 -678 -457 -648 ps 1
0.1 -1000 -1125 -970 -1095 -940 -1065 ps 1
NOTE 10: The
maximum
limit
for this parameter is not a device limit. The device will operate with a greater value
for this parameter, but system performance (bus turnaround) will degrade accordingly.
NOTE 11: MIN (t
CL
, t
CH
) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as
provided to the device (i.e. this value can be greater than the minimum specification limits for t
CL
and t
CH
).
NOTE 12: t
QH
= t
HP
– t
QHS
, where:
t
HP
= minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (t
CH
, t
CL
).
t
QHS
accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel
to n-channel variation of the output drivers.
NOTE 13: t
DQSQ
: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the
output drivers as well as output slew rate mismatch between DQS / DQS# and associated DQ in any given cycle.
NOTE 14: t
DAL
= WR + RU{ t
RP
[ns] / t
CK
[ns] }, where RU stands for round up.WR refers to the t
WR
parameter stored
in the MRS. For t
RP
, if the result of the division is not already an integer, round up to the next highest integer. t
CK
refers to the application clock period.
NOTE 15: The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In
case of clock frequency change during precharge power-down.
NOTE 16: ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from t
AOND
, which is interpreted
as 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
NOTE 17: ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is
when the bus is in high impedance. Both are measured from t
AOFD
, which is interpreted differently per speed bin.
For DDR2-1066, if t
CK
(avg) = 1.875 ns is assumed, t
AOFD
is 0.9375 ns (= 0.5 x 1.875 ns) after the second trailing
clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock
edges.
AS4C32M16D2A-25BIN
Alliance Memory Inc.
511 Taylor Way, San Carlos, CA 94070 TEL: [phone] FAX: [phone]
Alliance Memory Inc. reserves the right to change products or specification without notice
Rev.1.2
30
Jun./2014