Datasheet

Table 26. IDD specification parameters and test conditions
(V
DD
= 1.8V ± 0.1V, T
OPER
= -40~95 °C)
Parameter & Test Condition Symbol
-18I -25I -3I
Unit
Max.
Operating one bank active-precharge current:
t
CK
=t
CK
(min), t
RC
= t
RC
(min), t
RAS
= t
RAS
(min); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
I
DD0
95 90 85 mA
Operating one bank active-read-precharge current:
I
OUT
= 0mA; BL = 4, CL = CL (min), AL = 0; t
CK
= t
CK
(min),t
RC
= t
RC
(min),
t
RAS
= t
RAS
(min), t
RCD
= t
RCD
(min);CKE is HIGH, CS# is HIGH between
valid commands;Address bus inputs are switching; Data pattern is same
as I
DD4W
I
DD1
105 100 95 mA
Precharge power-down current:
All banks idle;t
CK
=t
CK
(min); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
I
DD2P
8 8 8 mA
Precharge quiet standby current:
All banks idle; t
CK
=t
CK
(min); CKE is HIGH, CS# is HIGH; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING
I
DD2Q
40 35 35 mA
Precharge standby current:
All banks idle; t
CK
= t
CK
(min); CKE is HIGH, CS# is HIGH; Other control
and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
I
DD2N
45 40 40 mA
Active power-down current:
All banks open; t
CK
=t
CK
(min); CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs are
FLOATING
MRS(A12)=0
I
DD3P
30 30
30
mA
MRS(A12)=1 15 15
15
mA
Active standby current:
All banks open; t
CK
= t
CK
(min), t
RAS
= t
RAS
(max), t
RP
= t
RP
(min); CKE is
HIGH, CS# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
I
DD3N
65 60 60 mA
Operating burst write current:
All banks open,continuous burst writes; BL = 4, CL = CL (min), AL = 0;
t
CK
= t
CK
(min), t
RAS
= t
RAS
(max), t
RP
= t
RP
(min); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are switching; Data
bus inputs are switching
I
DD4W
175 135 125 mA
Operating burst read current:
All banks open, continuous burst reads, I
OUT
= 0mA; BL = 4, CL = CL
(min), AL = 0; t
CK
= t
CK
(min), t
RAS
= t
RAS
(max), t
RP
= t
RP
(min); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
I
DD4R
175 135 125 mA
Burst refresh current:
t
CK
= t
CK
(min); refresh command at every t
RFC
(min) interval; CKE is
HIGH, CS# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
I
DD5
100 90 85 mA
Self refresh current:
CK and CK# at 0V; CKE  0.2V;Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
I
DD6
6 6 6 mA
Operating bank interleave read current:
All bank interleaving reads, I
OUT
= 0mA; BL = 4, CL = CL (min), AL =t
RCD
(min) - 1 x t
CK
(min); t
CK
= t
CK
(min), t
RC
= t
RC
(min), t
RRD
= t
RRD
(min), t
RCD
= t
RCD
(min); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs.Data pattern is
same as IDD4R
I
DD7
220 180 160 mA
AS4C32M16D2A-25BIN
Alliance Memory Inc.
511 Taylor Way, San Carlos, CA 94070 TEL: [phone] FAX: [phone]
Alliance Memory Inc. reserves the right to change products or specification without notice
Rev.1.2
25
Jun./2014