Datasheet

z Off-chip drive (OCD) impedance adjustment
DDR2 SDRAM supports driver calibration feature and the following flow chart is an example of sequence.Every
calibration mode command should be followed by “OCD calibration mode exit” before any other command being
issued.All MR should be programmed before entering OCD impedance adjustment and ODT (On Die Termination)
should be carefully controlled depending on system environment.
Figure 4. OCD impedance adjustment sequence
Start
EMRS:OCD calibration mode exit
EMRS:Drive(1)
DQ &DQS HIGH;DQS# LOW
Test
EMRS:OCD calibration mode exit
EMRS:Enter Adjust Mode
BL=4 code input to all DQs
Inc, Dec, or NOP
EMRS:OCD calibration mode exit
EMRS:Drive(0)
DQ &DQS LOW;DQS# HIGH
Test
EMRS:OCD calibration mode exit
EMRS:Enter Adjust Mode
BL=4 code input to all DQs
Inc, Dec, or NOP
EMRS:OCD calibration mode exit
End
EMRS:OCD calibration mode exit
ALL OK
Before entering OCD impedance adjustment, all MR should be programmed and
ODT should be carefully controlled depending on system environment
ALL OK
AS4C32M16D2A-25BIN
Alliance Memory Inc.
511 Taylor Way, San Carlos, CA 94070 TEL: [phone] FAX: [phone]
Alliance Memory Inc. reserves the right to change products or specification without notice
Rev.1.2
13
Jun./2014