Datasheet

AS4C32M16D1A-C&I
50 Rev. 1.0 Mar. /2015
Figure 35. Self Refresh Mode
CK
CK
CKE
NOP
COMMAND
Don’t Care
VALID
t
CK
AR
NOP
Clock must be stable before
Exiting Self Refresh mode
Enter Self Refresh
mode
t
CH
t
CL
t
IS
t
IS
t
IH
t
IS
t
IS
t
IH
ADDR
VALID
DQS
DQ
DM
t
IS
t
IH
t
RP*
t
XSNR/
t
XSRD**
Exit Self Refresh
mode
* = Device must be in the “All banks idle” state prior to entering Self Refresh mode
** = tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CK) is
required before a READ command can be applied.