Datasheet

3. Clocks (CK, CK#) need to be started and stabilized for at least 10ns or 5t
CK
(which is larger) before CKE
goes active. Since CKE is a synchronous signal, the corresponding setup time to clock (t
IS
) must be met.
Also a Deselect command must be registered (with t
IS
set up time to clock) at clock edge Td. Once the CKE
registered “high” after Reset, CKE needs to be continuously registered “high” until the initialization sequence
is finished, including expiration of t
DLLK
and t
ZQinit
.
4. The DDR4 SDRAM keeps its on-die termination in high-impedance state as long as Reset# is asserted.
Further, the SDRAM keeps its on-die termination in high impedance state after Reset# deassertion until
CKE is registered high. The ODT input signal may be in undefined state until t
IS
before CKE is registered
high. When CKE is registered high, the ODT input signal may be statically held at either low or high. If R
TT_NOM
is to be enabled in MR1 the ODT input signal must be statically held low. In all cases, the ODT input signal
remains static until the power up initialization sequence is finished, including the expiration of t
DLLK
and t
ZQinit.
5. After CKE is being registered high, wait minimum of Reset CKE Exit time, t
XPR
, before issuing the first MRS
command to load mode register. (t
XPR
=Max(t
XS
, 5nCK)]
6. Issue MRS Command to load MR3 with all application settings (To issue MRS command to MR3, provide
“ low” to BG0, “high” to BA1, BA0)
7. Issue MRS command to load MR6 with all application settings (To issue MRS command to MR6, provide
“low” to BA0, “high” to BG0, BA1)
8. Issue MRS command to load MR5 with all application settings (To issue MRS command to MR5, provide
“low” to BA1, “high” to BG0, BA0)
9. Issue MRS command to load MR4 with all application settings (To issue MRS command to MR4, provide
“Low” to BA1, BA0, “High” to BG0)
10. Issue MRS command to load MR2 with all application settings (To issue MRS command to MR2, provide
“Low” to BG0, BA0, “High” to BA1)
11. Issue MRS command to load MR1 with all application settings (To issue MRS command to MR1, provide
“Low” to BG0, BA1, “High” to BA0)
12. Issue MRS command to load MR0 with all application settings (To issue MRS command to MR0, provide
“Low” to BG0, BA1, BA0)
13. Issue ZQCL command to starting ZQ calibration.
14. Wait for both t
DLLK
and t
ZQinit
completed.
15. The DDR4 SDRAM is now ready for Read/Write training (include V
REF
training and Write leveling).
CK#
Tb Tc Td Te Tf Tg Th Ti TjTa
RESET#
CK
t
CKSRX
Tk
200μs 500μs
t
XPR
t
MRD
t
MRD
t
MRD
t
MOD
t
ZQinit
MRSNote 1 MRS MRS MRS ZQCL Note 1 VALID
MRxMRx MRx MRx VALID
VALID
Static LOW in case R
TT_NOM
is enabled at time Tg, otherwise static HIGH or LOW
VDD,VDDQ
CMD
CKE
BA
ODT
RTT
10ns
t
IS
t
IS
t
IS
t
IS
NOTE 1. From time point "Td" until "Tk " DES commands must be applied between MRS and ZQCL commands.
NOTE 2. MRS Commands must be issued to all Mode Registers that have defined settings.
VPP
VALID
DON'T CARETIME BREAK
t
DLLK
Figure 4. RESET# and Initialization Sequence at Power-on Ramping
AS4C256M16D4
Confidential
- 9 of 201 -
Rev.1.0 Aug.2019