Datasheet
Read Preamble
DDR4 supports a programmable read preamble. The 1 t
CK
and 2 t
CK
Read preamble is selected via MR4 A[11].
Read preamble modes of 1 t
CK
and 2 t
CK
are shown as follows:
DQS, DQS#
DQ
DQ
Preamble
Preamble
DQS, DQS#
D1
D2 D3
D4
D5
D6
D0
D1
D2 D3
D4
D5
D6
D0
D7
D7
1t
CK
toggle
2t
CK
toggle
Figure 82. 1t
CK
vs. 2t
CK
READ Preamble Mode
Read Preamble Training
DDR4 supports Read preamble training via MPR reads; that is, Read preamble training is allowed only when
the DRAM is in the MPR access mode. The Read preamble training mode can be used by the DRAM controller
to train or "read level" its DQS receivers. Read preamble training is entered via an MRS command (MR4 A[10]
= 1 is enabled and MR4 A[10] = 0 is disabled). After the MRS command is issued to enable Read preamble
training, the DRAM DQS signals are driven to a valid level by the time t
SDO
is satisfied. During this time, the data
bus DQ signals are held quiet, i.e. driven high. The DQS signal remains driven low and the DQS# signal remains
driven high until an MPR Page0 Read command is issued (MPR0 through MPR3 determine which pattern is
used), and when CAS latency (CL) has expired, the DQS signals will toggle normally depending on the burst
length setting. To exit Read preamble training mode, an MRS command must be issued, MR4 A[10] = 0.
DQ (Quiet or driven)
CL
DQS, DQS#
NOTE 1. Read Preamble Training mode is enabled by MR4 A10 = [1]
READ
t
SDO
MRS
1
DQS drive
Figure 83. READ Preamble Training
Table 36. AC Timing Table
Symbol
Parameter
Min.
Max.
Unit
t
SDO
Delay from MRS Command to Data Strobe Drive Out
-
t
MOD
+ 9ns
AS4C256M16D4
Confidential
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Rev.1.0 Aug.2019