Datasheet
Programmable Preamble
The DQS preamble can be programmed to one or the other of 1 t
CK
and 2 t
CK
preamble; selectable via MRS
(MR4 A[12:11]). The 1 t
CK
preamble applies to all speed-Grade and The 2 t
CK
preamble is valid for DDR4-2400
/2666 speed-Grade.
Write Preamble
DDR4 supports a programmable write preamble. The 1 t
CK
or 2 t
CK
Write Preamble is selected via MR4 A[12].
Write preamble modes of 1 t
CK
and 2 t
CK
are shown below.
When operating in 2 t
CK
Write preamble mode in MR2 CWL (CAS Write Latency), CWL of 1
st
Set needs to
be incremented by 2 nCK and CWL of 2
nd
Set does not need increment of it. t
WTR
must be increased by one
clock cycle from the t
WTR
required in the applicable speed bin table. WR must be programmed to a value one
or two clock cycle(s), depending on available settings, greater than the WR setting required per the applicable
speed bin table.
DQS, DQS#
DQ
DQ
Preamble
Preamble
DQS, DQS#
D1
D2 D3
D4
D5
D6
D0
D1
D2 D3
D4
D5
D6
D0
D7
D7
2 tCK mode
1 tCK mode
Figure 78. 1t
CK
vs. 2t
CK
WRITE Preamble Mode
The timing diagrams contained in t
CCD
=4 (AL=PL=0), t
CCD
=5 and t
CCD
=6 (AL=PL=0) illustrate 1 and 2 t
CK
preamble scenarios for consecutive write commands with t
CCD
timing of 4, 5 and 6 nCK, respectively. Setting
t
CCD
to 5nCK is not allowed in 2 t
CK
preamble mode.
t
CCD = 4
CK#
CK
DQS,DQS#
DQ
WL
WRWR
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3
Preamble
1t
CK
mode
t
CCD = 4
CK#
CK
DQS,DQS#
DQ
WL
WRWR
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1
Preamble
2t
CK
mode
Figure 79. t
CCD
=4 (AL=PL=0)
AS4C256M16D4
Confidential
- 85 of 201 -
Rev.1.0 Aug.2019