Datasheet

DDR4 Key Core Timing
DESWRITE DES DES WRITE DES DES DES WRITE DES DES DES
NOTE 1. tCCD_S : CAS#-to-CAS# delay (short) : Applies to consecutive CAS# to different Bank Group (i.e., T0 to T4).
NOTE 2. tCCD_L : CAS#-to-CAS# delay (long) : Applies to consecutive CAS# to the same Bank Group (i.e., T4 to T10).
T0 T1 T2 T3 T4 T5 T9 T10 T11
T12 T13
CK#
CK
ADDR
DON'T CARE
t
CCD_L
Bank Group
(GB)
CMD
Bank
t
CCD_S
TIME BREAK
BG a BG b BG b
Bank c Bank c Bank c
Col n
Col n Col n
Figure 72. t
CCD
Timing (WRITE to WRITE Example)
DESREAD DES DES READ DES DES DES READ DES DES DES
NOTE 1. tCCD_S : CAS#-to-CAS# delay (short) : Applies to consecutive CAS# to different Bank Group (i.e., T0 to T4)
NOTE 2. tCCD_L : CAS#-to-CAS# delay (long) : Applies to consecutive CAS# to the same Bank Group (i.e., T4 to T10)
T0 T1 T2 T3 T4 T5 T9 T10 T11
T12 T13
CK#
CK
ADDR
DON'T CARE
t
CCD_L
Bank Group
(GB)
CMD
Bank
t
CCD_S
TIME BREAK
BG a BG b BG b
Bank c Bank c Bank c
Col n Col n Col n
Figure 73. t
CCD
Timing (READ to READ Example)
DESACT DES DES ACT DES DES DES ACT DES DES DES
NOTE 1. tRRD_S: ACTIVATE to ACTIVATE Command period (short) : Applies to consecutive ACTIVATE Commands to different
Bank Group (i.e., T0 to T4).
NOTE 2. tRRD_L: ACTIVATE to ACTIVATE Command period (long) : Applies to consecutive ACTIVATE Commands to the different
Banks of the same Bank Group (i.e., T4 to T10).
T0 T1 T2 T3 T4 T5 T9 T10 T11
T12 T13
CK#
CK
ADDR
DON'T CARE
t
RRD_L
Bank Group
(GB)
CMD
Bank
t
RRD_S
TIME BREAK
BG a BG b BG b
Bank c Bank c Bank c
Row Row Row
Figure 74. t
RRD
Timing
AS4C256M16D4
Confidential
- 83 of 201 -
Rev.1.0 Aug.2019