Datasheet

MPR Refresh Waveforms
TIME BREAK
MRS
1
PREA DES REF
2
DES DES DES DES DES DES VALID VALID
CK#
CK
CMD
ADDR
Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tc0T0 Tc1 Tc2 Tc3
VALIDVALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID
NOTE 1. Multi-Purpose Registers Read/Write Enable (MR3 A2 = 1)
- Redirect all subsequent read and writes to MPR locations
NOTE 2. 1x Refresh is only allowed when MPR mode is Enable.
Don't Care
Tc4
VALID
VALID
t
RP
MPR
Enable
t
MOD
t
RFC
Figure 69. Refresh Command Timing
TIME BREAK
DESRD DES DES DES DES DES DES DES DES REF
2
DES
CK#
CK
CMD
CKE
DQS#
DQS
ADDR
PL + AL + CL
DQs
T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5T0 Ta6 Ta7 Ta8
VALIDADD
1
VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID
UI2 UI3 UI4 UI5 UI6 UI7
NOTE 1. Address setting
- A[1:0] = “00”b (data burst order is fixed starting at nibble, always 00b here)
- A[2]= “0”b (For BL=8, burst order is fixed at 0,1,2,3,4,5,6,7)
- BA1 and BA0 indicate the MPR location
- A10 and other address pins are don’t care including BG0. A12 is don’t care when MR0 A[1:0] = “00” or “10” ,
and must be ‘1’b when MR0 A[1:0] = “01”
NOTE 2. 1x Refresh is only allowed when MPR mode is Enable.
Don't Care
UI0 UI1
Ta9
DES
VALID
t
RFC
(4+1)+Clocks
DQS#
DQS
DQ
UI2 UI3UI0 UI1
BL=8
BC=4
Figure 70. Read to Refresh Command Timing
TIME BREAK
DESWR DES DES REF
2
DES DES DES DES DES DES DES
CK#
CK
CMD
CKE
DQS#
DQS
ADDR
DQ
T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6T0 Ta7 Ta8 Ta9
VALIDADD
1
VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID
NOTE 1. Address setting - BA1 and BA0 indicate the MPR location - A [7:0] = data for MPR
- A10 and other address pins are don’t care.
NOTE 2. 1x Refresh is only allowed when MPR mode is Enable.
Don't Care
Ta10
DES
VALID
t
WR_MPR
t
RFC
Figure 71. Write to Refresh Command Timing
AS4C256M16D4
Confidential
- 82 of 201 -
Rev.1.0 Aug.2019