Datasheet

MPR Write Waveforms
TIME BREAK
MRS
1
PREA DES WR DES DES RD DES DES DES DES DES
PL
3
+ AL + CL
Ta0 Ta1 Tb0 Tc0 Tc1 Tc2 Td0 Td1T0 Td2 Td3 Td4
VALIDVALID VALID ADD
2
VALID VALID ADD VALID VALID VALID VALID VALID
UI2 UI3 UI4 UI5 UI6 UI7
NOTE 1. Multi-Purpose Registers Read/Write Enable (MR3 A2 = 1)
NOTE 2. Address setting - BA1 and BA0 indicate the MPR location
- A [7:0] = data for MPR
- A10 and other address pins are don’t care.
NOTE 3. PL(Parity latency) is added to Data output delay when C/A parity latency mode is enabled.
Don't Care
t
RP
UI0 UI1
Td5
MPR
Enable
DES
VALID
t
MOD
t
WR_MPR
CK#
CK
CMD
CKE
DQS#
DQS
ADDR
DQ
Figure 67. MPR Write Timing and Write to Read Timing
TIME BREAK
DESWR DES DES WR DES DES DES DES DES DES DES
T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6T0 Ta7 Ta8 Ta9
VALIDADD
1
VALID VALID ADD
1
VALID VALID VALID VALID VALID VALID VALID
NOTE 1. Address setting
- BA1 and BA0 indicate the MPR location
- A [7:0] = data for MPR
- A10 and other address pins are don’t care.
Don't Care
Ta10
DES
VALID
t
WR_MPR
CK#
CK
CMD
CKE
DQS#
DQS
ADDR
DQ
Figure 68. MPR Back to Back Write Timing
AS4C256M16D4
Confidential
- 81 of 201 -
Rev.1.0 Aug.2019