Datasheet

MPR Writes
MPR access mode allows 8-bit writes to the MPR Page 0 using the address bus A[7:0]. Data bus inversion
(DBI) is not allowed during MPR Write operation. The DRAM will maintain the new written values unless re-
initialized or there is power loss.
The following steps are required to use the MPR to write to mode register MPR Page 0.
1. The DLL must be locked if enabled.
2. Precharge all; wait until t
RP
is satisfied.
3. MRS command to MR3 A[2] = 1 (enable MPR data flow) and MR3 A[1:0] = 00 (MPR Page 0); writes to 01,
10, and 11 are not allowed.
4. t
MRD
and t
MOD
must be satisfied.
5. Redirect all subsequent Write commands to specific MPRx location.
6. Issue WR or WRA command:
a. BA1 and BA0 indicate MPRx location
1) 00 = MPR0
2) 01 = MPR1
3) 10 = MPR2
4) 11 = MPR3
b. A[7:0] = data for MPR Page 0, mapped A[7:0] to UI[7:0].
c. Remaining address inputs, including A10, and BG0 are "Don’t Care"
7. t
WR_MPR
must be satisfied to complete MPR Write.
8. Steps 5 through 7 may be repeated to write additional MPRx locations.
9. After the last MPRx write, t
MPRR
must be satisfied prior to exiting.
10. Issue MRS command to exit MPR mode; MR3 A[2] = 0.
11. When the t
MOD
sequence is completed, the DRAM is ready for normal operation from the core (such as
ACT).
AS4C256M16D4
Confidential
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Rev.1.0 Aug.2019