Datasheet

TIME BREAK
DESRD DES DES DES DES DES DES DES DES WR DES
CK#
CK
CMD
CKE
DQS#
DQS
ADDR
PL
3
+ AL + CL
DQs
T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5T0 Ta6 Tb0 Tb1
VALID
ADD
1
VALID VALID VALID VALID VALID VALID VALID VALID
ADD
2
VALID
UI2 UI3 UI4 UI5 UI6 UI7
NOTE 1. Address setting
- A[1:0] = “00”b (data burst order is fixed starting at nibble, always 00b here)
- A[2]= “0”b (For BL=8, burst order is fixed at 0,1,2,3,4,5,6,7)
- BA1 and BA0 indicate the MPR location
- A10 and other address pins are don’t care including BG0. A12 is don’t care when MR0 A[1:0] = “00”, and must be ‘1’b when MR0 A[1:0] = “01”
NOTE 2. Address setting
- BA1 and BA0 indicate the MPR location
- A [7:0] = data for MPR
- A10 and other address pins are don’t care.
NOTE 3. PL(Parity latency) is added to Data output delay when C/A parity latency mode is enabled.
Don't Care
t
MPRR
UI0 UI1
Figure 66. MPR Read to Write Timing
AS4C256M16D4
Confidential
- 79 of 201 -
Rev.1.0 Aug.2019