Datasheet
MPR Read Waveforms
t
MOD
TIME BREAK
MRS
1
PREA DES RD DES DES DES DES DES DES MRS
3
VALID
4
CK#
CK
CMD
CKE
DQS#
DQS
ADDR
t
RP
PL
5
+ AL + CL
DQs
Ta0 Ta1 Tb0 Tc0 Tc1 Tc2 Tc3 Td0T0 Td1 Te0 Tf0
VALIDVALID VALID ADD
2
VALID VALID VALID VALID VALID VALID VALID VALID
UI0 UI1 UI2 UI5 UI6 UI7
MPR
Enable
NOTE 1. Multi-Purpose Registers Read/Write Enable (MR3 A2 = 1)
- Redirect all subsequent read and writes to MPR locations
NOTE 2. Address setting
- A[1:0] = “00”b (data burst order is fixed starting at nibble, always 00b here)
- A[2]= “0”b (For BL=8, burst order is fixed at 0,1,2,3,4,5,6,7)
- BA1 and BA0 indicate the MPR location
- A10 and other address pins are don't care including BG0. A12 is don't care when
MR0 A[1:0] = “00” or “10”, and must be ‘1’b when MR0 A[1:0] = “01”
NOTE 3. Multi-Purpose Registers Read/Write Disable (MR3 A2 = 0)
NOTE 4. Continue with regular DRAM command.
NOTE 5. PL(Parity latency) is added to Data output delay when C/A parity latency mode is enabled.
Don't Care
MPR
Disable
t
MOD
t
MPRR
Figure 64. MPR Read Timing
t
CCD_S
TIME BREAK
RDDES DES RD DES DES DES DES DES DES DES DES
PL
3
+ AL + CL
T1 T2 T5 Ta0 Ta1 Ta2 Ta3 Ta4T0 Ta5 Ta6 Ta7
ADD
2
VALID VALID ADD
2
VALID VALID VALID VALID VALID VALID VALID VALID
UI0 UI1 UI2 UI3 UI4 UI5
NOTE 1. tCCD_S = 4, Read Preamble = 1tCK
NOTE 2. Address setting
- A[1:0] = “00”b (data burst order is fixed starting at nibble, always 00b here)
- A[2]= “0”b (For BL=8, burst order is fixed at 0,1,2,3,4,5,6,7) (For BC=4, burst order is fixed at 0,1,2,3,T,T,T,T)
- BA1 and BA0 indicate the MPR location
- A10 and other address pins are don’t care including BG0. A12 is don't care when MR0 A[1:0] = “00” or “10”, and must be ‘1’b when MR0 A[1:0] = “01”
NOTE 3. PL(Parity latency) is added to Data output delay when C/A parity latency mode is enabled.
Don't Care
UI0 UI1 UI2 UI3
Ta8 Ta9
DES DES DES
Ta10
VALID VALID VALID
UI6 UI7 UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7
UI0 UI1 UI2 UI3
CK#
CK
CMD
CKE
DQS#
DQS
ADDR
DQ (BL=8:Fixed)
DQS#
DQS
DQ (BC=4:Fixed)
Figure 65. MPR Back to Back Read Timing
AS4C256M16D4
Confidential
- 78 of 201 -
Rev.1.0 Aug.2019