Datasheet

MPR Readout Staggered Format
Staggered format of data return is defined as the staggering of the MPR data across the lanes. In this mode,
an RD/RDA command is issued to a specific data pattern location and then the data is returned on the DQ
from each of the different data pattern locations. For the x4 configuration, an RD/RDA to data pattern location
0 will result in data from location 0 being driven on DQ0, data from location 1 being driven on DQ1, data from
location 2 being driven on DQ2, and so on, as shown below. Similarly, an RD/RDA command to data pattern
location 1 will result in data from location 1 being driven on DQ0, data from location 2 being driven on DQ1,
data from location 3 being driven on DQ2, and so on. Examples of different starting locations are also shown.
Table 33. MPR Readout Staggered Format, x4
It is expected that the DRAM can respond to back-to-back RD/RDA commands to the MPR for all DDR4
frequencies so that a sequence (such as the one that follows) can be created on the data bus with no bubbles
or clocks between read data. In this case, the system memory controller issues a sequence of RD(MPR0),
RD(MPR1), RD(MPR2), RD(MPR3), RD(MPR0), RD(MPR1), RD(MPR2), and RD(MPR3).
Table 34. MPR Readout Staggered Format, x4 – Consecutive Reads
For the x8 configuration, the same pattern is repeated on the lower nibble as on the upper nibble. READs to
other MPR data pattern locations follow the same format as the x4 case. A read example to MPR0 for x8 and
x16 configurations is shown below.
Table 35. MPR Readout Staggered Format, x8 and x16
x4 Read MPR0 Command
x4 Read MPR1 Command
x4 Read MPR2 Command
x4 Read MPR3 Command
Stagger
UI[7:0]
Stagger
UI[7:0]
Stagger
UI[7:0]
Stagger
UI[7:0]
DQ0
MPR0
DQ0
MPR1
DQ0
MPR2
DQ0
MPR3
DQ1
MPR1
DQ1
MPR2
DQ1
MPR3
DQ1
MPR0
DQ2
MPR2
DQ2
MPR3
DQ2
MPR0
DQ2
MPR1
DQ3
MPR3
DQ3
MPR0
DQ3
MPR1
DQ3
MPR2
Stagger
UI[7:0]
UI[15:8]
UI[23:16]
UI[31:24]
UI[39:32]
UI[47:40]
UI[55:48]
UI[63:56]
DQ0
MPR0
MPR1
MPR2
MPR3
MPR0
MPR1
MPR2
MPR3
DQ1
MPR1
MPR2
MPR3
MPR0
MPR1
MPR2
MPR3
MPR0
DQ2
MPR2
MPR3
MPR0
MPR1
MPR2
MPR3
MPR0
MPR1
DQ3
MPR3
MPR0
MPR1
MPR2
MPR3
MPR0
MPR1
MPR2
x8 Read MPR0 Command
x16 Read MPR0 Command
Stagger
UI[7:0]
Stagger
UI[7:0]
Stagger
UI[7:0]
DQ0
MPR0
DQ0
MPR0
DQ8
MPR0
DQ1
MPR1
DQ1
MPR1
DQ9
MPR1
DQ2
MPR2
DQ2
MPR2
DQ10
MPR2
DQ3
MPR3
DQ3
MPR3
DQ11
MPR3
DQ4
MPR0
DQ4
MPR0
DQ12
MPR0
DQ5
MPR1
DQ5
MPR1
DQ13
MPR1
DQ6
MPR2
DQ6
MPR2
DQ14
MPR2
DQ7
MPR3
DQ7
MPR3
DQ15
MPR3
AS4C256M16D4
Confidential
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Rev.1.0 Aug.2019