Datasheet

MPR Reads
MPR reads are supported using BL8 and BC4 modes. Burst length on-the-fly is not supported for MPR
reads. Data bus inversion (DBI) is not allowed during MPR Read operation; the device will ignore the Read
DBI enable setting in MR5 [A12] when in MPR mode. Read commands for BC4 are supported with a starting
column address of A[2:0] = 000 or 100. After power-up, the content of MPR Page 0 has the default values,
which are defined in MPR Data Format table. MPR page 0 can be rewritten via an MPR Write command. The
device maintains the default values unless it is rewritten by the DRAM controller. If the DRAM controller does
overwrite the default values (Page 0 only), the device will maintain the new values unless re-initialized or there
is power loss.
Timing in MPR mode:
 Reads (back-to-back) from Page 0 may use t
CCD_S
or t
CCD_L
timing between Read commands.
 Reads (back-to-back) from Pages 1, 2, or 3 may not use t
CCD_S
timing between Read commands; t
CCD_L
must
be used for timing between Read commands The following steps are required to use the MPR to read out the
contents of a mode register (MPR Page x, MPRy).
1. The DLL must be locked if enabled.
2. Precharge all; wait until t
RP
is satisfied.
3. MRS command to MR3 A[2] = 1 (Enable MPR data flow), MR3 A[12:11] = MPR read format, and MR3
A[1:0] MPR page.
a. MR3 A[12:11] MPR read format:
1) 00 = Serial read format
2) 01 = Parallel read format
3) 10 = Staggered read format
4) 11 = RFU
b. MR3[1:0] MPR page:
1) 00 = MPR Page 0
2) 01 = MPR Page 1
3) 10 = MPR Page 2
4) 11 = MPR Page 3
4. t
MRD
and t
MOD
must be satisfied.
5. Redirect all subsequent Read commands to specific MPRx location.
6. Issue RD or RDA command.
a. BA1 and BA0 indicate MPRx location:
1) 00 = MPR0
2) 01 = MPR1
3) 10 = MPR2
4) 11 = MPR3
b. A12/BC# = 0 or 1; BL8 or BC4 fixed-only, BC4 OTF not supported.
1) If BL = 8 and MR0 A[1:0] = 01, A12/BC# must be set to 1 during MPR Read commands.
c. A2 = burst-type dependant:
1) BL8: A2 = 0 with burst order fixed at 0, 1, 2, 3, 4, 5, 6, 7
2) BL8: A2 = 1 not allowed
3) BC4: A2 = 0 with burst order fixed at 0, 1, 2, 3, T, T, T, T
4) BC4: A2 = 1 with burst order fixed at 4, 5, 6, 7, T, T, T, T
d. A[1:0] = 00, data burst is fixed nibble start at 00.
e. Remaining address inputs, including A10, BG0 are "Don’t Care."
7. After RL = AL + CL, DRAM bursts data from MPRx location; MPR readout format determined by MR3
A[12:10] and MR3 A[1:0] .
8. Steps 5 through 7 may be repeated to read additional MPRx locations.
9. After the last MPRx Read burst, t
MPRR
must be satisfied prior to exiting.
10. Issue MRS command to exit MPR mode; MR3 A[2] = 0.
11. After the t
MOD
sequence is completed, the DRAM is ready for normal operation from the core (such as
ACT).
AS4C256M16D4
Confidential
- 74 of 201 -
Rev.1.0 Aug.2019